Systems for testing and packaging integrated circuits

• US 7,621,761 B2
• Filed: 07/20/2007
• Issued: 11/24/2009
• Est. Priority Date: 06/20/2000
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: NanoNexus, Inc.
• Inventors: Mok, Sammy, Chong, Fu Chiung, Milter, Roman
• Primary Examiner(s): HYEON, HAE M
• Application Number:
  US11/781,172
• Publication Number:
  US 20080090429A1
• Time in Patent Office: 858 Days
• Field of Search: 439/66, 439/81, 439/91, 439/591, 257/678
• US Class Current: 439/81
• CPC Class Codes: C23C 18/00 Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
• CPC Class Codes: C25D 7/00 Electroplating characterised by the article coated
• CPC Class Codes: G01R 1/06727 Cantilever beams
• CPC Class Codes: G01R 1/06755 Material aspects
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01045 Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: H05K 3/4092 Integral conductive tabs, i.e. conductive parts partly detached from the substrate

Abstract

Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed stress metal springs, defining a looped spring structure. The formed springs provide high pitch compliant electrical contacts for a wide variety of interconnection systems, including chip scale semiconductor packages, high density interposer connectors, and probe contactors. Several embodiments of massively parallel interface integrated circuit test assemblies are also disclosed, comprising one or more substrates having stress metal spring contacts, to establish connections between one or more separated integrated circuits on a compliant wafer carrier.

Claims

1. A contactor, comprising:

at least one stress metal spring formed on a surface of a substrate, the stress metal spring having an anchor portion attached to the substrate surface and a free portion extending away from the substrate surface, the stress metal spring comprising a plurality of layers that together impart an inherent level of stress to the spring which effects rotation of the free portion of the stress metal spring from the substrate surface by an effective rotation angle; and

at least one plated metal layer substantially covering the stress metal spring.

2. The contactor of claim 1, wherein the at least one plated metal layer comprises any of nickel, an alloy of nickel which is selected from the group comprising nickel iron, nickel cobalt, nickel cobalt iron, nickel molly, nickel tungsten, nickel iron tungsten, nickel cobalt tungsten, nickel rhodium, nickel cobalt manganese, nickel iron rhodium, nickel iron manganese, palladium, an alloy of palladium, palladium cobalt, gold, an alloy of gold, silver, rhodium, cobalt, an alloy of cobalt, tin, an alloy of tin, copper, an alloy of copper, and lead containing or lead free solder materials.

3. The contactor of claim 1, wherein the at least one plated metal layer is applied with any of electroplating, electroless plating, sputtering and evaporation.

4. The contactor of claim 1, wherein the at least one plated metal layer provides any of increased mechanical strength, reduced electrical resistance, increased resistance to mechanical wear and reduced debris pickup.

5. The contactor of claim 1, wherein the free portion of the at least one stress metal spring extends from the anchor portion to define a tip, and wherein the at least one plated metal layer envelopes at least a portion of the free portion of the at least one stress metal spring extending from the tip toward the anchor portion.

6. The contactor of claim 1, wherein the at least one stress metal spring provides an electrical connection to any of a printed wiring board, an integrated circuit, a chip scale package, and a solder ball.

7. The contactor of claim 1, wherein the at least one stress metal spring comprises a plurality the stress metal springs defining an array for providing any of tight pitch, vertical compliance, and planarity compliance.

8. The contactor of claim 1, wherein the contactor comprises any of an interposer, a separable connector, and an interface assembly.

9. The contactor of claim 1, wherein the substrate comprises any of an integrated circuit package, an integrated circuit device, and a printed circuit board.

10. A process for forming a contactor, comprising the steps of:

forming at least one stress metal spring on a surface of a substrate which, upon release from said surface, has an anchor portion and a free portion, the stress metal spring comprising a plurality of layers that together impart an inherent level of stress to the spring; and

releasing the free portion of the stress metal spring from the substrate surface, wherein the free portion of the stress metal spring rotates away from the substrate surface by an effective rotation angle due to the inherent level of stress; and

covering the stress metal spring with at least one plated metal layer.

11. The process of claim 10, wherein the at least one plated metal layer comprises any of nickel, an alloy of nickel which is selected from the group comprising nickel iron, nickel cobalt, nickel cobalt iron, nickel molly, nickel tungsten, nickel iron tungsten, nickel cobalt tungsten, nickel rhodium, nickel cobalt manganese, nickel iron rhodium, nickel iron manganese, palladium, an alloy of palladium, palladium cobalt, gold, an alloy of gold, silver, rhodium, cobalt, an alloy of cobalt, tin, an alloy of tin, copper, an alloy of copper, and lead containing or lead free solder materials.

12. The process of claim 10, wherein the covering step comprises any of electroplating, electroless plating, sputtering, and evaporation.

13. The process of claim 10, wherein the at least one plated metal layer provides any of increased mechanical strength, reduced electrical resistance, increased resistance to mechanical wear and reduced debris pickup.

14. The process of claim 10, wherein the free portion of the at least one stress metal spring extends from the anchor portion to define a tip, and wherein the at least one plated metal layer envelopes at least a portion of the free portion of the at least one stress metal spring extending from the tip toward the anchor portion.

15. The process of claim 10, further comprising the step of:

establishing an electrical connection between the at least one stress metal spring and any of a printed wiring board, an integrated circuit, a chip scale package, and a solder ball.

16. The process of claim 10, wherein the at least one stress metal spring comprises a plurality the stress metal springs defining an array for providing any of tight pitch, vertical compliance, and planarity compliance.

17. The process of claim 10, wherein the substrate and the at least one stress metal spring comprises any of an interposer, a separable connector, and an interface assembly.

18. The process of claim 10, wherein the substrate comprises any of an integrated circuit package, an integrated circuit device, and a printed circuit board.