Pseudo-differential output driver with high immunity to noise and jitter

• US 7,622,957 B2
• Filed: 02/21/2008
• Issued: 11/24/2009
• Est. Priority Date: 05/25/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: King, Greg
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/072,110
• Publication Number:
  US 20080211535A1
• Time in Patent Office: 642 Days
• Field of Search: 326/26, 326/27, 326/30, 326 82- 87
• US Class Current: 326/82
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018585 programmable

Abstract

Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage transistors and programmable impedance and on-die termination circuits. The pseudo-differential output driver consumes little circuit area and has low output capacitance.

Claims

1. A circuit for transmitting an output signal, said circuit comprising:

a first impedance operative to receive a first voltage, wherein said first impedance comprises first resistor circuitry whose resistance is adjustable responsive to a voltage of a first resistance control signal;

switching circuitry coupled to said first impedance, said switching circuitry comprising a first path and a second parallel path, said switching circuitry operative to receive first and second differential input signals at said first and second paths, respectively, and to generate said output signal at a node in only one of said paths, without generating another output signal in another of said paths, in response to receipt of said first and second differential input signals; and

a second impedance coupled to said switching circuitry and operative to receive a second voltage, wherein said second impedance comprises second resistor circuitry whose resistance is adjustable responsive to a voltage of a second resistance control signal.

2. The circuit of claim 1 further comprising:

a third impedance coupled to said output node and operative to receive said first voltage.

3. The circuit of claim 2 wherein said third impedance comprises third resistor circuitry whose resistance is adjustable responsive to a voltage of a third resistance control signal.

4. The circuit of claim 2 wherein:

said third impedance is coupled to said output signal through fourth resistor circuitry; and

said output signal is coupled to said second impedance through fifth resistor circuitry.

5. The circuit of claim 1 wherein:

said first path comprises first and second transistors coupled in series; and

said second path comprises third and fourth transistors coupled in series.

6. The circuit of claim 5 wherein:

gates of said first and second transistors are coupled to said first differential input signal; and

gates of said third and fourth transistors are coupled to said second differential input signal.

7. The circuit of claim 6 wherein:

said first and second transistors are complementary; and

said third and fourth transistors are complementary.

8. The circuit of claim 6 wherein:

said output signal is coupled to a connection between said third and fourth transistors.

9. The circuit of claim 1 wherein:

said first impedance further comprises a first transistor coupled in series to said first resistor circuitry; and

said second impedance further comprises a second transistor coupled in series to said second resistor circuitry.

10. A method for transmitting an output signal from a driver circuit, said method comprising:

receiving a first differential input signal at a first path;

receiving a second differential input signal at a second parallel path, said second differential input signal complementary to said first differential input signal;

driving said output signal at a node in only one of said paths, without driving another output signal in another of said paths, a voltage of said driven output signal being indicative of a difference in voltages of said first and second differential input signals; and

disabling first on-die termination circuitry coupled in series to said first and second parallel paths by applying a first enable/disable signal to said first on-die termination circuitry.

11. The method of claim 10 further comprising:

activating a first transistor and deactivating a second transistor responsive to a voltage of said first differential input signal, wherein said first and second transistors are coupled in series; and

activating a third transistor and deactivating a fourth transistor responsive to a voltage of said second differential input signal, wherein said third and fourth transistors are coupled in series.

12. The method of claim 11 wherein said activating said first transistor and said deactivating said second transistor couple said output signal to a source of substantially constant voltage through programmable impedance circuitry.

13. The method of claim 10 further comprising:

setting a resistance of first impedance circuitry coupled in series to said first and second parallel paths by applying a first control signal to said first impedance circuitry; and

setting a resistance of second impedance circuitry coupled in series to said first and second parallel paths by applying a second control signal to said second impedance circuitry.

14. The method of claim 13 further comprising:

enabling said first impedance circuitry by applying a first enable/disable signal to a transistor of said first impedance circuitry; and

enabling said second impedance circuitry by applying a second enable/disable signal to a transistor of said second impedance circuitry.

15. The method of claim 10 further comprising disabling second on-die termination circuitry coupled to said output signal by applying a second enable/disable signal to said second on-die termination impedance circuitry.

16. A system comprising:

a processor;

a memory controller;

a dynamic random access memory device comprising an array of memory cells and a circuit for transmitting an output signal, said circuit comprising;

a source of relatively low voltage;

a first impedance operative to receive a first voltage, wherein said first impedance comprises first resistor circuitry whose resistance is adjustable responsive to a voltage of a first resistance control signal;

switching circuitry coupled to said first impedance, said switching circuitry comprising a first path and a second parallel path, said switching circuitry operative to receive first and second differential input signals at said first and second paths, respectively, and to generate said output signal at a node in only one of said paths, without generating another output signal in another of said paths, in response to receipt of said first and second differential input signals; and

a second impedance coupled to said switching circuitry and operative to receive a second voltage, wherein said second impedance comprises second resistor circuitry whose resistance is adjustable responsive to a voltage of a second resistance control signal.

17. The system of claim 16 wherein:

said first path comprises first and second transistors coupled in series; and

said second path comprises third and fourth transistors coupled in series.

18. The system of claim 17 wherein:

said first and second transistors are coupled to said first differential input signal; and

said third and fourth transistors are coupled to said second differential input signal.

19. The system of claim 18 wherein said output signal is coupled to a connection between said third and fourth transistors.

20. A circuit for transmitting an output signal from a driver circuit, said circuit comprising:

means for receiving a first differential input signal at a first path;

means for receiving a second differential input signal at a second parallel path, said second differential signal complementary to said first differential signal;

means for driving said output signal at a node in only one of said paths, without driving another output signal in another of said paths, a voltage of said driven output signal being indicative of a difference in voltages of said first and second differential input signals; and

means for disabling first on-die termination circuitry coupled in series to said first and second parallel paths by applying a first enable/disable signal to said first on-die termination circuitry.