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Pattern-based DC offset correction

  • US 7,622,987 B1
  • Filed: 01/24/2008
  • Issued: 11/24/2009
  • Est. Priority Date: 01/25/2007
  • Status: Active Grant
First Claim
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1. A method for correcting one or more DC offsets in an amplifier, the method comprising:

  • slicing an output signal of a gain stage of the amplifier to generate a 1-bit sliced signal, wherein symbols of the 1-bit sliced signal comprises a first state or a second state, wherein slicing is performed by electronic hardware;

    determining the presence of one or more patterns associated with DC offsets from the output signal of the gain stage of the amplifier by analyzing the 1-bit sliced signal for run length, wherein a run length comprises a count of consecutive runs of the first state or the second state, wherein a run length of at least a threshold value for the first state or the second state is associated with a positive DC offset or a negative DC offset, respectively; and

    generating a correction to reduce the DC offset based at least partly on a count of the run length of the first state or the second state.

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