Memory device interface methods, apparatus, and systems

• US 7,623,365 B2
• Filed: 08/29/2007
• Issued: 11/24/2009
• Est. Priority Date: 08/29/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joe M.
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/847,113
• Publication Number:
  US 20090059641A1
• Time in Patent Office: 818 Days
• Field of Search: 365/63, 365/51, 365/189.02
• US Class Current: 365/63
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices

Abstract

Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die having a plurality of memory arrays disposed on the first memory die, the second memory die including a plurality of vias, wherein the plurality of vias are configured to allow the plurality of TWI to pass through the second memory die. The second memory die may be coupled to a second plurality of TWI. In this way, the interface chip may be used to communicatively couple the first memory die and the second memory die using the first and second plurality of TWI. Other apparatus, systems, and methods are included.

Claims

1. An apparatus comprising:

a substrate;

an interface chip disposed on the substrate;

a first memory die having at least one memory array disposed on the interface chip, the first memory die coupled to a first plurality of through wafer interconnects (TWI); and

a second memory die having at least one memory array disposed on the first memory die, the second memory die including a plurality of vias, wherein the plurality of vias are configured to allow the first plurality of TWI to pass through the second memory die, the second memory die being coupled to a second plurality of TWI, wherein the interface chip communicatively couples the first memory die and the second memory die using the first and second plurality of TWI.

2. The apparatus of claim 1, wherein the interface chip is configured to provide address and command data to access memory cells within the first and second memory dice.

3. The apparatus of claim 1, wherein the at least one memory array includes a DRAM array.

4. The apparatus of claim 3, wherein the interface chip is configured to perform sequencing of the DRAM array.

5. The apparatus of claim 1, wherein the interface chip is configured to perform power management of the apparatus, and wherein the interface chip is operated at a voltage sufficient to preclude error bit generation.

6. The apparatus of claim 1, wherein the interface chip comprises:

an input/output driver circuit.

7. The apparatus of claim 3, wherein the interface chip is configured to operate a refresh scheme to control error rates based on the type of DRAM array used in the first and second memory die.

8. The apparatus of claim 1, wherein the interface chip is configured to operate a refresh scheme to control error rates based on the signal characteristics of the first and second memory die.

9. The apparatus of claim 1, wherein the interface chip is programmable and configured to operate based on the type of the first and second memory die placed on top of it.

10. The apparatus of claim 1, wherein the interface chip is configured to operate a bad cell recovery scheme with respect to the at least one memory array.

11. The apparatus of claim 2, wherein the interface chip is configured to perform Error Check and Correction (ECC) during data communication between the first and second memory dice and a processor disposed on the substrate.

12. The apparatus of claim 1, the interface chip further comprising:

a diagnostic module and Built in Self-Test (BIST) module.

13. The apparatus of claim 3, the interface chip further comprising:

a pattern generator configured to generate test pattern signals that are used for testing and diagnostic analysis of the apparatus.

14. The apparatus of claim 13, wherein the test pattern signals are transmitted and received between I/O terminals of the interface chip and the DRAM array, and a training algorithm is executed to calculate an optimum timing for each input/output connection.

15. The apparatus of claim 1, wherein the at least one memory array comprises a NAND flash memory array.

16. The apparatus of claim 1, wherein the at least one memory array comprises a NOR flash memory array.

17. The apparatus of claim 1, wherein the first and second plurality of TWI extend in a vertical direction with respect to a plane including the second memory die, through the second memory die, to couple the first memory die to the interface chip.

18. The apparatus of claim 11, wherein the interface chip is disposed on the processor, and the processor comprises a multi-core processor disposed on the substrate.

19. The apparatus of claim 1, wherein the first and second TWI form at least part of a data bus, the data bus coupling the memory arrays in the first and second memory dice and the interface chip.

20. The apparatus of claim 1, wherein the plurality of memory arrays in the first and second memory dice include a column decoder and a row decoder.

21. The apparatus of claim 1, further comprising connection pins to couple the second memory die with the interface chip.

22. A system comprising:

a first memory die having a plurality of memory arrays, the first memory die coupled to a first plurality of through wafer interconnects (TWI);

a second memory die having the first memory die disposed over the second memory die and having a plurality of memory arrays, the second memory die coupled to a second plurality of TWI, the second memory die including a plurality of vias configured to allow the first plurality of TWI to pass through the second memory die;

an interface chip coupled to the first memory die and the second memory die using the first and second plurality of TWI, the first and second memory die disposed on the interface chip; and

a processing unit communicatively coupled to the interface chip, the first memory die, and the second memory die.

23. The system of claim 22, wherein the plurality of memory arrays includes a DRAM array.

24. The system of claim 22, wherein the plurality of memory arrays includes a NAND flash memory array.

25. The system of claim 22, wherein the plurality of memory arrays includes a NOR flash memory array.

26. The system of claim 22, wherein the interface chip further comprises a multiplexer/demultiplexer circuit and a memory controller.

27. The system of claim 26, wherein the memory controller is configured to control a DRAM memory array.

28. The system of claim 26, wherein the memory controller is configured to control a flash memory array.

29. The system of claim 26, further wherein the processor is coupled to the multiplexer/demultiplexer circuit.

30. The system of claim 22, wherein the interface chip further comprising a communication module to provide at least one of wired and wireless communication.

31. The system of claim 22, wherein the interface chip is embedded within the substrate.

32. A method comprising:

at least one of sending and receiving data between a processing unit and an interface chip including at least one of a multiplexer and demultiplexer circuit and a memory controller;

at least one of sending and receiving the data from the interface chip to a plurality of memory dice using a plurality of Through Wafer Interconnects (TWI);

the plurality of TWI passing through a plurality of vias formed in the memory dice; and

storing the data in the plurality of memory dice, wherein each of the plurality of memory dice includes at least one memory arrays.

33. The method of claim 32, wherein storing the data in the plurality of memory dice comprises:

storing the data in a DRAM array.