Reducing program disturb in non-volatile storage using early source-side boosting

• US 7,623,386 B2
• Filed: 12/12/2006
• Issued: 11/24/2009
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lutze, Jeffrey W., Dong, Yingda
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Hidalgo; Fernando N
• Application Number:
  US11/609,804
• Publication Number:
  US 20080137425A1
• Time in Patent Office: 1,078 Days
• Field of Search: 365/185.18, 365/185.02, 365/185.17, 365/185.26, 365/185.28
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure

Abstract

Program disturb is reduced in non-volatile storage by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a first boost mode is used when the selected word line is a lower or intermediate word line. In the first boost mode, boosting of the source and drain side channels is initiated concurrently. A second boost mode is used when the selected word line is a higher word line. In the second boost mode, boosting of the source side channel occurs early relative to the boosting of the drain side channel. Either boost mode include an isolation voltage which tends to isolate the source and drain side channels from one another.

Claims

1. A method for operating non-volatile storage, comprising:

boosting a first region of a substrate starting at a first time, a set of non-volatile storage elements is formed, at least in part, on the substrate, the set of non-volatile storage elements is associated with a set of word lines and includes at least one non-volatile storage element associated with a selected word line of the set of word lines;

applying an isolation voltage to at least one isolation word line in the set of word lines on a source side of the selected word line, the first region extends under a plurality of word lines on a source side of the isolation word line in the substrate;

boosting a second region of the substrate on a drain side of the isolation word line, the boosting of the second region starts at a second time which is after the first time, the second region extends under a plurality of word lines, including the selected word line, on the drain side of the isolation word line in the substrate; and

applying a program voltage to the selected word line, the program voltage is applied starting at a third time which is after the second time, and ending at a fourth time which is after the third time, where the first region is boosted between at least the first and third times and the second region is boosted between at least the second and third times, but not between the first and second times, and the isolation voltage is applied at least between the first and fourth times.

2. The method of claim 1, further comprising:

the boosting of the second region comprises raising a voltage applied to the plurality of word lines on the drain side of the isolation word line from an initial level to a final level, starting at the second time, and maintaining the voltage at the final level at least until the third time.

3. The method of claim 1, wherein:

the set of non-volatile storage elements comprises NAND strings which extend between a source side select gate line and a drain side select gate line, and the second region extends from the isolation word line to the drain side select gate line.

4. The method of claim 1, wherein:

the first and second regions are adjacent to the isolation word line, on opposite sides of the isolation word line.

5. The method of claim 1, wherein:

the first region is boosted between the first and fourth times, and the second region is boosted between the second and fourth times.

6. The method of claim 1, wherein:

the boosting the first region comprises raising a source side voltage applied to word lines of the set of word lines which are on the source side of the isolation word line to a source side higher level at the first time, and maintaining the source side voltage at the source side higher level at least until the third time; and

the boosting the second region comprises raising a drain side voltage applied to word lines of the set of word lines which are on the drain side of the isolation word line to a higher drain side level at the second time, and maintaining the drain side voltage at the higher drain side level at least until the third time.

7. The method of claim 1, wherein:

the boosting the first region comprises raising a source side voltage applied to word lines of the set of word lines which are on the source side of the isolation word line from 0 V to a source side higher level at the first time, and maintaining the source side voltage at the source side higher level between the first and fourth times; and

the boosting the second region comprises raising a drain side voltage applied to word lines of the set of word lines which are on the drain side of the isolation word line from 0 V to a drain side higher level at the second time, and maintaining the drain side voltage at the drain side higher level between the second and fourth times.

8. The method of claim 3, wherein:

the first region extends from the isolation word line to the source side select gate line.

9. A method for operating non-volatile storage, comprising:

applying pass voltages to first and second groups of non-volatile storage elements in a set of non-volatile storage elements, the first group comprising a plurality of series-connected programmed non-volatile storage elements and the second group comprising a plurality of series-connected unprogrammed non-volatile storage elements; and

applying a programming voltage to at least one non-volatile storage element in the set of non-volatile storage elements which is between the first and second groups, the applying pass voltages and the applying the programming voltage occur in a cycle of boosting and programming of a programming operation which comprises multiple cycles of boosting and programming, where the pass voltages are applied prior to the applying the programming voltage, the pass voltages are applied to the first group prior to being applied to the second group, and an isolation voltage is applied to at least one isolation non-volatile storage element in the set of non-volatile storage elements between the first and second groups.

10. The method of claim 9, wherein:

the set of non-volatile storage elements is formed, at least in part, on a substrate, the pass voltages applied to the first group boost a first region of the substrate, on a source side of the isolation non-volatile storage element, and the pass voltages applied to the second group boost a second region of the substrate, on a drain side of the isolation non-volatile storage element, the second region extends under the second group and is adjacent to the isolation non-volatile storage element.

11. The method of claim 9, wherein:

the pass voltages applied to the first group are applied using a first set of common voltage waveforms, and the pass voltages applied to the second group are applied use a second set of common voltage waveforms.

12. The method of claim 9, wherein:

the pass voltages are applied to the first and second groups of non-volatile storage elements via associated word lines.

13. The method of claim 9, wherein:

the set of non-volatile storage elements is provided in at least one NAND string which extends between a source side select gate and a drain side select gate.

14. The method of claim 13, wherein:

the first group extends from the source side select gate to the at least one isolation non-volatile storage element and the second group extends from the drain side select gate to the at least one isolation non-volatile storage element.

15. A method for operating non-volatile storage, comprising:

performing a cycle of boosting and programming of a programming operation which includes multiple cycles of boosting and programming, the programming operation involves nonvolatile storage elements in a set of non-volatile storage elements, the set of non-volatile storage elements is formed, at least in part, on a substrate, the set of non-volatile storage elements is associated with a set of word lines;

the performing the cycle of boosting and programming includes applying an isolation voltage to an isolation word line in the set of word lines, applying a programming voltage on a selected word line of the set of word lines, and prior to applying the programming voltage, initiating boosting of a first region of the substrate on a source side of the isolation word line and initiating boosting of a second region of the substrate on a drain side of the isolation word line; and

determining when to implement a delay of the initiating boosting of the second region relative to the initiating boosting of the first region in the cycle of boosting and programming based on a position of the selected word line in the set of word lines.

16. The method of claim 15, wherein:

the boosting of the second region of the substrate continues during the applying of the programming voltage on the selected word line.

17. The method of claim 15, wherein:

the boosting of the first region comprises applying a pass voltage to at least one word line in the set of word lines on the source side, and the boosting of the second region comprises applying a pass voltage to at least one other word line in the set of word lines on the drain side.

18. The method of claim 15, wherein:

the delay is implemented when the selected word line is within a specified number of word lines from a drain side of the set of non-volatile storage elements; and

the delay is not implemented when the selected word line is not within the specified number of word lines from the drain side, so that the initiating boosting of the first region occurs concurrently with the initiating boosting of the second region.

19. The method of claim 18, wherein:

the specified number of word lines is approximately 25% of the word lines of the set of word lines.

20. The method of claim 18, wherein:

the specified number of word lines consists of fewer than all word lines in the set of word lines.

21. The method of claim 15, wherein:

the set of non-volatile storage elements is provided in at least one NAND string which extends between a source side select gate and a drain side select gate.

22. The method of claim 21, wherein:

the non-volatile storage elements in the set of non-volatile storage elements are programmed in an order extending from the source side select gate to the drain side select gate.