Managing memory in a parallel processing environment

• US 7,624,248 B1
• Filed: 04/14/2006
• Issued: 11/24/2009
• Est. Priority Date: 04/14/2006
• Status: Active Grant

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Tilera Corporation (NVIDIA Corporation)
• Inventors: Agarwal, Anant, Wentzlaff, David
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US11/404,187
• Time in Patent Office: 1,320 Days
• Field of Search: 711/135, 711/202, 711/203, 711/154, 711/137, 711/133, 711/128, 711/130, 711/129, 711/170, 712/11, 712/10, 712/14, 712/19, 712/18, 712/15
• US Class Current: 711/202
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An integrated circuit comprises a plurality of tiles. Each tile comprises: a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled, and a translation lookaside buffer coupled to the switch to translate virtual memory addresses of switch instructions to physical memory addresses of the switch instructions.

Claims

1. An integrated circuit, comprising:

a plurality of tiles, each tile comprising

a processor,

a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled, and

a translation lookaside buffer coupled to the switch to translate virtual memory addresses of switch instructions to physical memory addresses of the switch instructions;

wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.

2. The integrated circuit of claim 1, wherein each tile further comprises a translation lookaside buffer coupled to the processor to translate virtual memory addresses of processor instructions to physical memory addresses of the processor instructions.

3. The integrated circuit of claim 1, wherein the switching circuitry is coupled to bypass paths that connect non-adjacent pipeline stages of the processor.

4. The integrated circuit of claim 1, wherein the switching circuitry is coupled to a buffer accessible by the processor.

5. The integrated circuit of claim 4, wherein the switching circuitry is coupled to a buffer accessible within a register name space of the processor.

6. The integrated circuit of claim 4, wherein the switching circuitry is coupled to a buffer accessible within a memory address space of the processor.

7. The integrated circuit of claim 4, wherein the switching circuitry is coupled to a buffer accessible within an input/output device name space of the processor.

8. The integrated circuit of claim 4, wherein the buffer comprises an input buffer configured to receive data over an input port of the switch.

9. The integrated circuit of claim 4, wherein the buffer comprises an output buffer configured to send data over an output port of the switch.

10. An integrated circuit, comprising:

a plurality of tiles, each tile comprising

a processor,

a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and

a memory interface coupled to at least one of the processor and the switch, configured to combine partial memory addresses to provide a physical memory address in a first mode, and configured to translate a virtual memory address to a physical memory address in a second mode.

11. The integrated circuit of claim 10, wherein combining partial memory addresses to provide a physical memory address comprises concatenating low order bits with high order bits to provide a physical memory address.

12. The integrated circuit of claim 11, wherein the low order bits comprise a virtual memory address.

13. The integrated circuit of claim 10, wherein the memory interface comprises a translation lookaside buffer configured to store information for translating a virtual memory address to a physical memory address.

14. The integrated circuit of claim 13, wherein the memory interface is configured to update information stored in the translation lookaside buffer in response to a translation fault.

15. The integrated circuit of claim 10, wherein the memory interface comprises a multiplexer configured to select a combined physical memory address or a translated physical memory address based on a signal indicating the first or the second mode.

16. An integrated circuit, comprising:

a plurality of tiles, each tile comprising

a processor,

a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles,

a memory coupled to the processor,

a cache manager including circuitry to transfer data between the memory and an external memory through the switch, and

a direct memory access engine coupled to the processor and including circuitry to transfer data between the memory and the external memory through the switch;

wherein the switch comprises multiple switch points each including respective switching circuitry to forward data over respective data paths and the cache manager and the direct memory access engine are coupled to a common switch point and the common switch point is reserved for transferring data among memories of tiles and one or more external memories coupled to the tiles.

17. The integrated circuit of claim 16, wherein switching circuitry for the common switch point is configured to forward data based at least in part on information included in the data to be forwarded.

18. The integrated circuit of claim 16, wherein the cache manager comprises a state machine configured to transfer cache lines between the memory and the external memory.

19. The integrated circuit of claim 18, wherein the direct memory access engine is configured to transfer multiple cache lines between the memory and the external memory.

20. The integrated circuit of claim 19, wherein the direct memory access engine is configured to transfer multiple cache lines in response to a request received from the processor.

21. The integrated circuit of claim 19, wherein the direct memory access engine is configured to fetch data from the external memory to the memory based on memory access history of the processor.

22. The integrated circuit of claim 19, wherein the direct memory access engine is configured to flush data from the memory to the external memory based on memory access history of the processor.

23. An integrated circuit, comprising:

a plurality of tiles, each tile comprising

a processor,

a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles,

a memory coupled to the processor,

a direct memory access engine including circuitry to transfer data between the memory and a memory external to the tile through the switch, and

a translation look-aside buffer coupled to the direct memory access engine to translate virtual memory addresses to physical memory addresses;

wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.

24. The integrated circuit of claim 23, wherein the switching circuitry is coupled to bypass paths that connect non-adjacent pipeline stages of the processor.

25. The integrated circuit of claim 23, wherein the switching circuitry is coupled to a buffer accessible by the processor.

26. The integrated circuit of claim 25, wherein the switching circuitry is coupled to a buffer accessible within a register name space of the processor.

27. The integrated circuit of claim 25, wherein the switching circuitry is coupled to a buffer accessible within a memory address space of the processor.

28. The integrated circuit of claim 25, wherein the switching circuitry is coupled to a buffer accessible within an input/output device name space of the processor.

29. The integrated circuit of claim 25, wherein the buffer comprises an input buffer configured to receive data over an input port of the switch.

30. The integrated circuit of claim 25, wherein the buffer comprises an output buffer configured to send data over an output port of the switch.

31. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:

processing instructions in a processor of a tile;

forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled; and

translating virtual memory addresses of switch instructions to physical memory addresses of the switch instructions;

wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.

32. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:

processing instructions in a processor of a tile;

forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles; and

based on information indicating either a first mode or a second mode, combining partial memory addresses to provide a physical memory address in the first mode, and translating a virtual memory address to a physical memory address in the second mode.

33. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch, and a memory coupled to the processor, the method comprising:

processing instructions in a processor of a tile;

forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles;

transferring data between the memory and an external memory through the switch according to a caching scheme to maintain a cache for the tile; and

transferring data between the memory and the external memory through the switch according to a direct memory transfer scheme to transfer data while the processor is performing another task;

wherein the switch comprises multiple switch points each including respective switching circuitry to forward data over respective data paths and the cache manager and the direct memory access engine are coupled to a common switch point, and the common switch point is reserved for transferring data among memories of tiles and one or more external memories coupled to the tiles.

34. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch and a local memory coupled to the processor, the method comprising:

processing instructions in a processor of a tile;

forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles; and

transferring data between the local memory and memory of another tile through the switch according to a direct memory transfer scheme to transfer data while the processor is performing another task.

35. The method of claim 34, wherein each tile further comprises an interface coupled to the processor and a direct memory access engine that enables the processor to identify data to be transferred by the direct memory access engine.

36. The method of claim 35, wherein the interface comprises at least one register that the processor writes to and the direct memory access engine reads from.

37. The method of claim 34, wherein the direct memory access engine communicates with a direct memory access engine of the other tile to transfer the data.

38. The method of claim 34, wherein the local memory and the memory of the other tile each include at least some memory locations configured as a cache for data from an external memory coupled to the tiles.

39. The method of claim 38, wherein the transferred data comprises a cache line.

40. The method of claim 39, wherein the direct memory access engine is configured to invalidates a cache line that is transferred to another tile.

41. The method of claim 38, wherein the local memory comprises multiple memories configured as multiple levels in a multi-level cache.

42. The method of claim 41, further comprising updating multiple levels in the local memory when the processor writes data into the multi-level cache.

43. The method of claim 38, wherein the direct memory access engine is configured to transfers data into a portion of the local memory configured to be protected from eviction by cached data from the external memory.

44. The method of claim 34, wherein the direct memory access engine is configured to transfers data between the local memory and memory of the other tile after determining whether the transfer is allowed.

45. The method of claim 44, wherein determining whether the transfer is allowed comprises determining whether access to a source location of the data is allowed.

46. The method of claim 44, wherein determining whether the transfer is allowed comprises determining whether access to a destination location of the data is allowed.

47. The method of claim 46, wherein determining whether access to a destination location of the data is allowed comprises determining whether access to the memory of the other tile is allowed.

48. The method of claim 44, wherein the direct memory access engine includes a buffer storing information identifying a plurality of tiles and information indicating whether access to an identified tile is allowed.

49. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch, and a memory coupled to the processor, the method comprising:

processing instructions in a processor of a tile;

forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles;

transferring data between the memory coupled to the processor and a memory external to the tile through the switch according to a direct memory transfer scheme to transfer data while the processor is performing another task; and

translating virtual memory addresses to be transferred according to the direct memory access transfer scheme to physical memory addresses;

wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.