Managing memory in a parallel processing environment
First Claim
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1. An integrated circuit, comprising:
- a plurality of tiles, each tile comprisinga processor,a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled, anda translation lookaside buffer coupled to the switch to translate virtual memory addresses of switch instructions to physical memory addresses of the switch instructions;
wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.
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Abstract
An integrated circuit comprises a plurality of tiles. Each tile comprises: a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled, and a translation lookaside buffer coupled to the switch to translate virtual memory addresses of switch instructions to physical memory addresses of the switch instructions.
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Citations
49 Claims
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1. An integrated circuit, comprising:
a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled, and a translation lookaside buffer coupled to the switch to translate virtual memory addresses of switch instructions to physical memory addresses of the switch instructions; wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit, comprising:
a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and a memory interface coupled to at least one of the processor and the switch, configured to combine partial memory addresses to provide a physical memory address in a first mode, and configured to translate a virtual memory address to a physical memory address in a second mode. - View Dependent Claims (11, 12, 13, 14, 15)
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16. An integrated circuit, comprising:
a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, a memory coupled to the processor, a cache manager including circuitry to transfer data between the memory and an external memory through the switch, and a direct memory access engine coupled to the processor and including circuitry to transfer data between the memory and the external memory through the switch; wherein the switch comprises multiple switch points each including respective switching circuitry to forward data over respective data paths and the cache manager and the direct memory access engine are coupled to a common switch point and the common switch point is reserved for transferring data among memories of tiles and one or more external memories coupled to the tiles. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. An integrated circuit, comprising:
a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, a memory coupled to the processor, a direct memory access engine including circuitry to transfer data between the memory and a memory external to the tile through the switch, and a translation look-aside buffer coupled to the direct memory access engine to translate virtual memory addresses to physical memory addresses; wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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31. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:
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processing instructions in a processor of a tile; forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles, according to a switch instruction indicating an input port to which each of multiple output ports of the switch is to be coupled; and translating virtual memory addresses of switch instructions to physical memory addresses of the switch instructions; wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.
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32. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor and a switch, the method comprising:
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processing instructions in a processor of a tile; forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles; and based on information indicating either a first mode or a second mode, combining partial memory addresses to provide a physical memory address in the first mode, and translating a virtual memory address to a physical memory address in the second mode.
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33. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch, and a memory coupled to the processor, the method comprising:
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processing instructions in a processor of a tile; forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles; transferring data between the memory and an external memory through the switch according to a caching scheme to maintain a cache for the tile; and transferring data between the memory and the external memory through the switch according to a direct memory transfer scheme to transfer data while the processor is performing another task; wherein the switch comprises multiple switch points each including respective switching circuitry to forward data over respective data paths and the cache manager and the direct memory access engine are coupled to a common switch point, and the common switch point is reserved for transferring data among memories of tiles and one or more external memories coupled to the tiles.
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34. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch and a local memory coupled to the processor, the method comprising:
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processing instructions in a processor of a tile; forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles; and transferring data between the local memory and memory of another tile through the switch according to a direct memory transfer scheme to transfer data while the processor is performing another task. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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49. A method for processing instructions in an integrated circuit, the integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch, and a memory coupled to the processor, the method comprising:
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processing instructions in a processor of a tile; forwarding data received over data paths from other tiles to the processor and to switches of other tiles, and forwarding data received from the processor to switches of other tiles; transferring data between the memory coupled to the processor and a memory external to the tile through the switch according to a direct memory transfer scheme to transfer data while the processor is performing another task; and translating virtual memory addresses to be transferred according to the direct memory access transfer scheme to physical memory addresses; wherein the processor is a pipelined processor and the switching circuitry is coupled to a plurality of stages of the pipeline.
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Specification