Method and system of control flow graph construction
First Claim
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1. A processor, comprising:
- fetch logic configured to retrieve a plurality of instructions from a memory, wherein the plurality of instructions are from a first native instruction set of the processor; and
decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions,wherein the processor is configurable to execute the plurality of instructions and to construct a control flow graph for the plurality of instructions,wherein when the processor is configured to construct the control flow graph, each instruction in the first native instruction set of the processor is associated with a micro-sequence configured to generate a portion of the control flow graph corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the control flow graph is constructed, andwhen the processor is configured to execute the plurality of instructions, each instruction in a subset of the first native instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when the micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction,wherein a micro-sequence is one or more instructions from a second native instruction set of the processor.
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Abstract
A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.
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Citations
24 Claims
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1. A processor, comprising:
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fetch logic configured to retrieve a plurality of instructions from a memory, wherein the plurality of instructions are from a first native instruction set of the processor; and decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions, wherein the processor is configurable to execute the plurality of instructions and to construct a control flow graph for the plurality of instructions, wherein when the processor is configured to construct the control flow graph, each instruction in the first native instruction set of the processor is associated with a micro-sequence configured to generate a portion of the control flow graph corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the control flow graph is constructed, and when the processor is configured to execute the plurality of instructions, each instruction in a subset of the first native instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when the micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction, wherein a micro-sequence is one or more instructions from a second native instruction set of the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for constructing a control flow graph for a plurality of instructions, comprising:
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configuring a processor to construct the control flow graph instead of executing instructions in a first native instruction set of the processor, wherein configuring comprises associating each instruction in the first native instruction set of the processor with a micro-sequence configured to generate a portion of the control graph corresponding to the instruction; responsive to fetching and decoding each instruction in the plurality of instructions, executing the micro-sequence associated with the instruction, wherein the control graph is constructed; and reconfiguring the processor to execute instructions in the instruction set after the control graph is constructed, wherein reconfiguring comprises associating each instruction in a subset of the first native instruction set with a micro-sequence configured to perform a function of the instruction, wherein all other instructions in the first native instruction set are executed directly by the processor, wherein a micro-sequence is one or more instructions from a second native instruction set of the processor. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A system, comprising:
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a memory; a first processor; and a second processor coupled to the first processor, the second processor comprising; fetch logic configured to retrieve a plurality of instructions from the memory, wherein the plurality of instructions are from a first native instruction set of the second processor; and decode logic coupled to the fetch logic, wherein the decode logic is configured to decode the plurality of instructions, wherein the second processor is configurable to execute the plurality of instructions and to construct a control flow graph for the plurality of instructions, wherein when the second processor is configured to construct the control flow graph, each instruction in the first native instruction set of the second processor is associated with a micro-sequence configured to generate a portion of the control flow graph corresponding to the instruction and the decode logic, responsive to decoding each instruction in the plurality of instructions, causes the micro-sequence associated with each instruction in the plurality of instructions to be executed, wherein the control flow graph is constructed, and when the second processor is configured to execute the plurality of instructions, each instruction in a subset of the instruction set is associated with a micro-sequence configured to perform a function of the instruction and the decode logic causes each instruction in the plurality of instructions to be executed, wherein when a micro-sequence is associated with the instruction, the micro-sequence is executed to perform the function of the instruction, wherein a micro-sequence is one or more instructions from a second native instruction set of the second processor. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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Specification