Methods of making spintronic devices with constrained spintronic dopant

• US 7,625,767 B2
• Filed: 03/16/2007
• Issued: 12/01/2009
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Dukovski, Ilija, Halilov, Samed, Hytha, Marek, Mears, Robert J., Huang, Xiangyang, Yiptong, Jean Augustin Chan Sow Fook
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US11/687,430
• Publication Number:
  US 20070238274A1
• Time in Patent Office: 991 Days
• Field of Search: 438/3, 438 22- 24, 438 48- 52
• US Class Current: 438/3
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01F 1/401 diluted
• CPC Class Codes: H01F 1/405 of IV type, e.g. Ge1-xMnx
• CPC Class Codes: H01F 10/3213 Exchange coupling of magnetic semiconductor multilayers, e.g. MnSe/ZnSe superlattices semiconductor materials for use in semiconductor devices H01L29/12
• CPC Class Codes: H01F 10/3268 the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
• CPC Class Codes: H01F 41/301 for applying ultrathin or granular layers ultrathin or granular layers H01F10/007
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/15 Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices such structures applied for the control of light G02F1/017, applied in semiconductor lasers H01S5/34
• CPC Class Codes: H01L 29/66984 Devices using spin polarized carriers

Abstract

A method is for making a spintronic device and may include forming at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant. The spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, the repeating structure of a superlattice may not be needed.

Claims

1. A method for making a spintronic device comprising:

forming at least one superlattice; and

forming at least one electrical contact coupled to the at least one superlattice;

the at least one superlattice comprising a plurality of groups of layers with each group of layers comprising

a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice,

at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and

at least one spintronic dopant monolayer adjacent the at least one non-semiconductor monolayer and constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer.

2. The method according to claim 1 wherein said at least one spintronic dopant monolayer comprises a transition metal dopant.

3. The method according to claim 1 wherein said at least one spintronic dopant monolayer comprises a Manganese dopant.

4. The method according to claim 2 wherein the transition metal dopant comprises at least one of Manganese, Iron, and Chromium.

5. The method according to claim 1 wherein said at least one spintronic dopant monolayer comprises a rare earth element dopant.

6. The method according to claim 5 wherein the rare earth element dopant comprises a rare earth lanthanide.

7. The method according to claim 1 wherein the at least one non-semiconductor monolayer comprises Oxygen.

8. The method according to claim 1 wherein the at least one-non-semiconductor monolayer comprises at least one of Oxygen, Nitrogen, Fluorine, Carbon-Oxygen, and Sulphur.

9. The methods according to claim 1 wherein the semiconductor comprises Silicon.

10. The method according to claim 1 wherein the semiconductor comprises a semiconductor selected from the group comprising Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

11. The method according to claim 1 wherein forming the at least one superlattice comprises forming a pair of superlattices;

and further comprising;

providing a substrate carrying the pair of superlattices in spaced apart relation to define a source and a drain;

forming a channel between the source and drain; and

forming a gate adjacent the channel so that the spintronic device defines a spintronic field effect transistor.

12. The method according to claim 1 wherein forming the at least one superlattice comprises forming a pair of superlattices;

and further comprising;

providing a substrate carrying the pair of superlattices in spaced apart relation; and

forming a spacer between the pair of superlattices so that the spintronic device defines a spintronic valve.

13. The method according to claim 1 wherein the at least one superlattice exhibits a Curie temperature of at least as high as room temperature.

14. A method for making a spintronic device comprising:

forming at least one superlattice; and

forming at least one electrical contact coupled to the at least one superlattice;

the at least one superlattice comprising a plurality of groups of layers with each group of layers comprising

a plurality of stacked base Silicon monolayers defining a base Silicon portion having a crystal lattice,

at least one Oxygen monolayer constrained within the crystal lattice of adjacent base Silicon portions, and

at least one spintronic dopant monolayer adjacent the at least one non-semiconductor monolayer and constrained within the crystal lattice of the base Silicon portion by the at least one Oxygen monolayer.

15. The method according to claim 14 wherein the at least one spintronic dopant monolayer comprises at least one of a transition metal, and a rare earth element dopant.

16. The method according to claim 14 wherein forming the at least one superlattice comprises forming a pair of superlattices;

and further comprising;

providing a substrate carrying the pair of superlattices in spaced apart relation to define a source and a drain;

forming a channel between the source and drain; and

forming a gate adjacent the channel so that the spintronic device defines a spintronic field effect transistor.

17. The method according to claim 14 wherein forming the at least one superlattice comprises forming a pair of superlattices;

and further comprising;

providing a substrate carrying the pair of superlattices in spaced apart relation; and

forming a spacer between the pair of superlattices so that the spintronic device defines a spintronic valve.

18. The method according to claim 14 wherein the at least one superlattice exhibits a Curie temperature of at least as high as room temperature.

19. A method for making spintronic device comprising:

forming a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice;

forming at least one non-semiconductor monolayer constrained within the crystal lattice;

providing at least one spintronic dopant monolayer adjacent the at least one non-semiconductor monolayer and constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer; and

forming an electrical contact coupled to the base semiconductor portion.

20. The method according to claim 19 wherein the at least one spintronic dopant monolayer comprises at least one of a transition metal and a rare earth element dopant.

21. The method according to claim 19 wherein the at least one non-semiconductor monlayer comprises at least one of Oxygen, Nitrogen, Fluorine, Carbon-Oxygen, and Sulphur.

22. The method according to claim 19 wherein the semiconductor comprises a semiconductor selected from the group comprising Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

23. The method according to claim 19 further comprising providing a substrate carrying the base semiconductor portion.

24. The method according to claim 19 wherein the base semiconductor portion exhibits a Curie temperature of at least as high as room temperature.