Power MOS device with improved gate charge performance

• US 7,625,793 B2
• Filed: 09/26/2005
• Issued: 12/01/2009
• Est. Priority Date: 12/20/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Calafut, Daniel S.
• Primary Examiner(s): Lindsay, Jr.; Walter L
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US11/236,112
• Publication Number:
  US 20060024890A1
• Time in Patent Office: 1,527 Days
• Field of Search: 438/259, 438/289, 438/430, 438/301, 438/589, 438/212, 438/268, 438/270, 257/E21.429, 257/E21.444, 257/E21.41
• US Class Current: 438/212
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

Claims

1. A method comprising:

(a) forming a body region of a first conductivity type in a semiconductor substrate having a drain region of a second conductivity type;

(b) forming a source region of the second conductivity type in the body region;

(c) forming a trench with a bottom and walls in the semiconductor substrate;

(d) implanting ions of the first conductivity type into the bottom of the trench using a zero angle ion implantation process to form an implant region within the drain region such that the implant region is of the second conductivity type but has a lower doping concentration than a doping concentration of the drain region;

(e) performing a high temperature process to diffuse out the implanted ions such that the implant region surrounds the bottom of the trench and extends up the walls of trench but does not contact the body region; and

(f) forming a gate in the trench such that the implant region overlaps the gate along the walls of the trench.

2. The method of claim 1 wherein the step of performing the high temperature process comprises annealing.

3. The method of claim 1 wherein the high temperature process is carried out at a temperature in the range of about 900-1,500°

F.

4. The method of claim 1 wherein the source region is formed adjacent to upper portions of the trench walls.

5. The method of claim 1 further comprising forming a gate dielectric along the walls of the trench prior to forming the gate.

6. The method of claim 1 wherein the drain region comprises a first doped region and a second doped region, the first doped region extending under and having a higher doping concentration than the second doped region.

7. The method of claim 6 wherein the implant region is fully embedded within the second doped region of the drain region.

8. The method of claim 6 wherein the trench extends into and terminates within the second doped region.