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Power MOS device with improved gate charge performance

  • US 7,625,793 B2
  • Filed: 09/26/2005
  • Issued: 12/01/2009
  • Est. Priority Date: 12/20/1999
  • Status: Expired due to Fees
First Claim
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1. A method comprising:

  • (a) forming a body region of a first conductivity type in a semiconductor substrate having a drain region of a second conductivity type;

    (b) forming a source region of the second conductivity type in the body region;

    (c) forming a trench with a bottom and walls in the semiconductor substrate;

    (d) implanting ions of the first conductivity type into the bottom of the trench using a zero angle ion implantation process to form an implant region within the drain region such that the implant region is of the second conductivity type but has a lower doping concentration than a doping concentration of the drain region;

    (e) performing a high temperature process to diffuse out the implanted ions such that the implant region surrounds the bottom of the trench and extends up the walls of trench but does not contact the body region; and

    (f) forming a gate in the trench such that the implant region overlaps the gate along the walls of the trench.

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