Method of forming a shielded gate field effect transistor
First Claim
1. A method of forming a FET comprising:
- providing a semiconductor region of a first conductivity type with an epitaxial layer of the first conductivity extending over the semiconductor region;
performing a first silicon etch to form an upper trench portion extending into and terminating within the epitaxial layer;
forming protective material extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion;
performing a second silicon etch to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, the lower trench portion being narrower than the upper trench portion; and
performing a two-pass angled implant of dopants of the first conductivity type to form a silicon region of first conductivity type along sidewalls of the lower trench portion, the protective material blocking the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.
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0 Petitions
Accused Products
Abstract
A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.
49 Citations
18 Claims
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1. A method of forming a FET comprising:
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providing a semiconductor region of a first conductivity type with an epitaxial layer of the first conductivity extending over the semiconductor region; performing a first silicon etch to form an upper trench portion extending into and terminating within the epitaxial layer; forming protective material extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion; performing a second silicon etch to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, the lower trench portion being narrower than the upper trench portion; and performing a two-pass angled implant of dopants of the first conductivity type to form a silicon region of first conductivity type along sidewalls of the lower trench portion, the protective material blocking the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of forming a MOSFET comprising:
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providing a substrate of a first conductivity type with an epitaxial layer of a first conductivity extending over the substrate; performing a first silicon etch to form an upper trench portion extending into and terminating within the epitaxial layer; forming protective material extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion; performing a second silicon etch to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the substrate, the lower trench portion being narrower than the upper trench portion; performing a two-pass angled implant of dopants of the first conductivity type to form a silicon region of first conductivity type along sidewalls of the lower trench portion, the protective material blocking the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion; forming a shield dielectric lining sidewalls and bottom surface of the lower trench portion; forming a shield electrode in the lower trench portion; forming a gate dielectric layer along sidewalls of the upper trench portion; and forming a gate electrode in the upper trench portion over but insulated from the shield electrode. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A MOSFET comprising:
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a trench having a lower portion and an upper portion, the lower portion being narrower than the upper portion, the trench extending into a semiconductor region; a shield electrode in the lower portion of the trench, the shield electrode being insulated from the semiconductor region by a shield dielectric; a gate electrode in the upper portion of the trench, the gate electrode being over but insulated from the shield electrode; wherein the semiconductor region comprises; a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over the substrate; a body region of a second conductivity type in the epitaxial layer; a source region of the first conductivity type in the body region, the source region and an interface between the body region and the substrate defining a channel region; and a silicon region of the first conductivity type extending along sidewalls of the lower portion of the trench and into a lower portion of the channel region, the silicon region having a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the trench. - View Dependent Claims (17, 18)
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Specification