Semiconductor device and method for fabricating the same

• US 7,626,229 B2
• Filed: 01/10/2005
• Issued: 12/01/2009
• Est. Priority Date: 02/16/2004
• Status: Expired due to Fees

• Current Assignee: Collabo Innovations, Inc. (Wi-LAN Inc.)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Miyata, Satoe, Mizokuchi, Shuji
• Primary Examiner(s): Gurley, Lynne A.
• Assistant Examiner(s): MATTHEWS, COLLEEN ANN
• Application Number:
  US11/030,945
• Publication Number:
  US 20050179082A1
• Time in Patent Office: 1,786 Days
• Field of Search: 257328-330, 257/E29.2, 257/E27.112, 257/E21.41, 257/E29.262
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes: a semiconductor substrate; a first semiconductor region formed in the reverse surface region of the semiconductor substrate and including a first conductivity type impurity; a second semiconductor region formed on the first semiconductor region in the semiconductor substrate and including a second conductivity type impurity; a third semiconductor region formed on the second semiconductor region in the semiconductor substrate and including a first conductivity type impurity; a trench passing through the second and third semiconductor regions and reaching the first semiconductor region; and a gate insulating film formed along the wall face of the trench; a gate electrode formed on the gate insulating film in the trench. Further, a pocket region including a second conductivity type impurity of which peak concentration is higher than that of the second semiconductor region is formed by a side of the trench between the second semiconductor region and the third semiconductor region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a first conductivity type drain region provided in a lower part of said semiconductor substrate;

a second conductivity type substrate region provided on said drain region in said semiconductor substrate;

a first conductivity type source region provided on said substrate region in said semiconductor substrate;

a trench formed in said semiconductor substrate and reaching said drain region;

a gate insulating film provided at least on a side wall of said trench;

a gate electrode provided on said gate insulating film in said trench;

a second conductivity type pocket region provided between said substrate region and said source region and being in contact with said source region;

an insulating film formed in said trench to cover said gate electrode and having an upper end located lower than an upper surface of said semiconductor substrate;

a source electrode provided above said source region; and

a second conductivity type high concentration substrate region formed so as to be adjacent to said source region on said substrate region in said semiconductor substrate and having an impurity concentration higher than that of said substrate region,

wherein said gate insulating film is in contact with said substrate region and said pocket region at said side wall of said trench, and

said source electrode is in contact with an upper surface of said source region, and in contact with a portion of a side surface of said source region which is located above said upper end of said insulating film in said trench.

2. The semiconductor device of claim 1, wherein said pocket region is formed only under a portion of said source region, the portion being close to said side wall of said trench.

3. The semiconductor device of claim 1, wherein

said pocket region is formed under an entire portion of said source region.

4. The semiconductor device of claim 1, wherein said pocket region has a peak of impurity concentration higher than that of said substrate region.

5. The semiconductor device of claim 1, wherein said drain region includes:

a first conductivity type high concentration drain region; and

a first conductivity type low concentration drain region provided on said high concentration drain region.

6. The semiconductor device of claim 1, wherein

said source electrode is made of a suicide film.

7. The semiconductor device of claim 1, wherein

an upper end of a part where said gate electrode is in contact wit said gate insulating film is located upper than a boundary between said source region and said pocket region.

8. The semiconductor device of claim 1, wherein a peak of impurity concentration of said pocket region is located close to said gate insulating film in a direction perpendicular to the depth direction of said trench in said semiconductor substrate.

9. The semiconductor device of claim 1, wherein said substrate region is to be a channel region.