Apparatus and method for hysteretic boost DC-DC converter

• US 7,626,370 B1
• Filed: 09/21/2007
• Issued: 12/01/2009
• Est. Priority Date: 09/21/2007
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Mei, Tawen, Song, Chunping
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US11/859,645
• Time in Patent Office: 802 Days
• Field of Search: 323/222, 323/223, 323/225, 323/268, 323/271, 323/282, 323/285, 323/288, 323349-351
• US Class Current: 323/282
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence

Abstract

A boost hysteretic DC-DC converter is provided. The converter includes a power switch, a hysteretic comparator, an inductor, an output capacitor, and a resistive device. The resistive device is coupled to the bottom of the output capacitor, so that the output voltage is equal to the sum of the capacitor voltage and the voltage across the resistive device. The resistance of the resistance device is sufficiently large that the output voltage ripple is in phase with the inductor current.

Claims

1. A circuit for regulation, comprising:

boost converter circuitry, including;

a hysteretic comparator having at least a first input, a second input, and an output, wherein the first input of the hysteretic comparator is coupled to an output node;

a power switch that is coupled between a switch node and another node; and

a resistive device that is coupled to said another node, wherein the boost converter circuitry is arranged to operate with an output capacitor coupled between the output node and said another node, the resistive device is arranged to provide a portion of an output voltage at the output node, and wherein the resistive device has a resistance that is sufficiently large that an output voltage ripple of the output voltage is out of phase with an output capacitor voltage ripple of a voltage across the output capacitor.

2. The circuit of claim 1, wherein

the power switch is arranged to selectively couple the switch node to said another node based, at least in part, on whether the hysteretic comparator is tripped.

3. The circuit of claim 1, wherein

the power switch is a power transistor having at least a gate that is coupled to the output of the hysteretic comparator, a drain that is coupled to the switch node, and a source that is coupled to said another node.

4. The circuit of claim 1, wherein

the resistive device is arranged such that the output voltage is substantially equal to a sum of a voltage across the output capacitor and a voltage across the resistive device.

5. The circuit of claim 1, wherein

the boost converter circuitry is arranged to operate in conjunction with an inductor that is coupled between an input node and the switch node, the boost converter circuitry is arranged to drive a load, and

wherein the resistive device is arranged such that a current through the resistive device is substantially equal to an inductor current of the inductor minus an load current of the load, regardless of whether the power switch is open or closed.

6. The circuit of claim 1, wherein

the resistor is coupled between said another node and yet another node, and

wherein the boost converter circuitry is arranged to drive a load that is coupled between the output node and said yet another node.

7. The circuit of claim 1, wherein

the boost converter circuitry is arranged to convert an input voltage at an input node into the output voltage, and

wherein the resistance of the resistive device is sufficiently large to meet the following inequality:

$R_s><br><br>\frac{V_o}{V_{\mathrm{in}}}·<br><br>\frac{C}{R_o}·<br><br>L,$

where R_s represents the total equivalent resistance of the resistive device, V_O represents the output voltage, V_in represents the input voltage, C represents the capacitance of an output capacitor, and where L represents the inductance of an inductor that is coupled between the input node and the switch node.

8. A circuit for regulation, comprising:

a boost converter, including;

a hysteretic comparator having at least a first input that is coupled to a first node, a second input that is coupled to a second node, and an output that is coupled to a third node;

a capacitor that is coupled between the first node and the fourth node;

a resistive device that is coupled between the fourth node and a fifth node, such that a voltage drop because between the first node and the fifth node includes a sum of a voltage across the capacitor and a voltage across the resistive device; and

a power transistor having at least a gate that is coupled to the third node, a source that is coupled to the fourth node, and a drain that is coupled to a sixth node.

9. The circuit of claim 8, wherein

the resistive device has a resistance that is sufficiently large that an output voltage ripple of an output voltage at the first node is out of phase with an output capacitor voltage ripple of the voltage across the capacitor, and such that the output voltage ripple is in phase with an inductor current.

10. The circuit of claim 8, wherein

the boost converter further includes a device that is coupled between the sixth node and the first node,

wherein the device is at least one of a diode or a synchronous switch.

11. The circuit of claim 8, further comprising:

a reference voltage circuit having at least an output that is coupled to the second node.

12. The circuit of claim 8, wherein

the fifth node is ground.

13. The circuit of claim 8, further comprising:

a load that is coupled between the first node and the fifth node.

14. The circuit of claim 8, further comprising

a voltage divider that is coupled between the output voltage and first input of the hysteretic comparator, such that the first input of the hysteretic comparator is coupled to the output voltage via the voltage divider, wherein the boost converter further includes a de-glitcher that is coupled between the third node and the gate of the power transistor, so that the gate of the power transistor is coupled to the third node via the de-glitcher.

15. The circuit of claim 8, wherein

the boost converter further includes an inductor that is coupled between a seventh node and the sixth node.

16. The circuit of claim 15, wherein

a resistance of the resistive device is sufficiently large to meet the following inequality:

$R_s><br><br>\frac{V_o}{V_{\mathrm{in}}}·<br><br>\frac{C}{R_o}·<br><br>L,$

where R_s represents the total equivalent resistance of the resistive device, V_O represents the output voltage, V_in represents a voltage at the seventh node, C represents the capacitance of the capacitor, and where L represents the inductance of the inductor.

17. A method for regulation, comprising:

converting an input voltage at an input node into an output voltage at an output node that is greater than the input voltage, including;

comparing the output voltage with a reference voltage, such that the comparison includes hysteresis;

employing a result of the comparison to selectively transfer energy from an inductor that is coupled to the input node to an output capacitor that is coupled to the output node; and

adding a ramp to the output voltage such that the output voltage ripple is out of phase with an output capacitor ripple of a voltage across the output capacitor, and such that an output ripple of the output voltage is substantially proportional to an inductor current that is associated with the inductor.

18. The method of claim 17, wherein

comparing the output voltage with the reference voltage includes:

providing a feedback voltage from the output voltage;

asserting a comparison output signal if the feedback voltage is less than a reference voltage minus half of a hysteretic band of the comparison, wherein the comparison output signal indicates the result of the comparison; and

de-asserting the comparison output signal if the feedback voltage is greater than the reference voltage plus half of the hysteretic band of the comparison.

19. The method of claim 17, wherein

selectively transferring energy from the inductor to the output capacitor includes selecting coupling a switch node to another node based on the result of the comparison.

20. The method of claim 19, wherein

adding the ramp to the output voltage includes employing a resistor that is coupled between said another node and yet another node,

wherein the output capacitor is coupled between said another node and the output node, and

wherein the inductor is coupled between the input node and the switch node.