Hall-effect device with merged and/or non-merged complementary structure

• US 7,626,377 B2
• Filed: 02/18/2008
• Issued: 12/01/2009
• Est. Priority Date: 02/18/2008
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Morales, Gilberto, Kilian, Wayne T.
• Primary Examiner(s): Tang; Minh N.
• Assistant Examiner(s): Nguyen; Tung X
• Application Number:
  US12/032,763
• Publication Number:
  US 20090206424A1
• Time in Patent Office: 652 Days
• Field of Search: 324/117.H, 324/117.R, 324/126, 324/765, 324/158.1, 324/763, 257/401, 257/421, 257/426, 732/042.6, 438 14- 18
• US Class Current: 324/117.00H
• CPC Class Codes: G01R 33/07 Hall effect devices
• CPC Class Codes: H01L 29/82 controllable by variation of the magnetic field applied to the device
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 52/101 Semiconductor Hall-effect devices
• CPC Class Codes: H10N 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 MRAM devices H10B61/00

Abstract

A Hall-effect device with a merged and/or non-merged complementary structure in order to cancel stress induced offsets includes an n-type epitaxial Hall element and a p-type Hall element. The p-type Hall element can be implanted directly on top of the n-type epitaxial Hall element. The merged Hall elements can be biased in parallel to provide a zero-bias depletion layer throughout for isolation. The output of the p-type Hall element can be connected to the geometrically corresponding output of the n-type epitaxial Hall element through a suitable resistance. The output signal can be taken at the outputs of the n-type element. The Hall-effect device can be constructed utilizing standard processes.

Claims

1. A Hall-effect apparatus having a complementary structure comprising;

an n-type epitaxial Hall element, wherein said n-type epitaxial Hall element comprises a first pair of sensing contacts disposed on a substrate layer, said n-type epitaxial Hall element surrounded vertically by an isolation layer;

a p-type Hall element comprising a second pair of sensing contacts implanted on a region of said n-type epitaxial layer isolated from said n-type epitaxial Hall element, wherein said n-type epitaxial Hall element and said p-type Hall element are biased in a parallel arrangement in order to provide similar quiescent output voltages thereof; and

an insulation layer associated with a plurality of conductors disposed above said n-type epitaxial Hall element and said p-type Hall element, thereby geometrically connecting said second pair of sensing contacts to said first pair of sensing contacts through a resistive network and providing an output signal thereof through said first pair of sensing contacts.

2. The apparatus of claim 1 wherein said n-type epitaxial Hall element and said p-type Hall element comprise a pair of electrical bias contacts.

3. The apparatus of claim 1 wherein said n-type epitaxial Hall element is arranged in a non-merged configuration with respect to said p-type Hall element.

4. The apparatus of claim 1 wherein said resistive network is configured to restrict variation in a magnitude of said output signal in response to temperature changes.

5. The apparatus of claim 1 wherein said output signal comprises a voltage signal indicative of said n-type epitaxial Hall element.

6. The apparatus of claim 1 wherein said n-type epitaxial Hall element and said p-type Hall element are configured on a semiconductor body comprising silicon and utilizing a silicon integrated circuit technology.

7. A Hall-effect apparatus having a merged complementary structure, comprising;

an n-type epitaxial Hall element comprising a first pair of sensing contacts disposed on a substrate layer, wherein said n-type epitaxial Hall element is surrounded vertically by an isolation layer;

a p-type Hall element comprising a second pair of sensing contacts implanted directly on said n-type epitaxial Hall element, wherein said n-type epitaxial Hall element and said p-type Hall element are biased in a parallel arrangement in order to provide a zero-bias depletion layer throughout for isolation; and

an insulation layer associated with a plurality of conductors disposed above said p-type Hall element thereby geometrically connecting said second pair of sensing contacts to geometrically corresponding said first pair of sensing contacts through a suitable resistive network and taking an output signal through said first pair of sensing contacts.

8. The apparatus of claim 7 wherein said n-type epitaxial Hall element and said p-type Hall element comprise a pair of electrical bias contacts.

9. The apparatus of claim 7 wherein said n-type epitaxial Hall element is merged with said p-type Hall element so that an individual stress-induced offset is associated with destructively combining the offsets of said n-type epitaxial Hall element and said p-type Hall element.

10. The apparatus of claim 7 wherein said resistive network is configured to restrict a variation in a magnitude of said output signal in response to temperature changes.

11. The apparatus of claim 7 wherein said output signal comprises a voltage signal indicative of said n-type epitaxial Hall element.

12. The apparatus of claim 7 wherein said n-type epitaxial Hall element and said p-type Hall element are configured on a semiconductor body comprising silicon and utilizing a silicon integrated circuit technology.

13. The apparatus of claim 7 wherein:

said n-type epitaxial Hall element and said p-type Hall element comprise a pair of electrical bias contacts;

said n-type epitaxial Hall element is merged with said p-type Hall element so that an individual stress-induced offset is associated with destructively combining the offsets of said n-type epitaxial Hall element and said p-type Hall element; and

said resistive network is configured to restrict a variation in a magnitude of said output signal in response to temperature changes.

14. The apparatus of claim 13 wherein said output signal comprises a voltage signal indicative of said n-type epitaxial Hall element and wherein said n-type epitaxial Hall element and said p-type Hall element are configured on a semiconductor body comprising silicon and utilizing a silicon integrated circuit technology.

15. A method of configuring a Hall-effect apparatus to comprise a merged complementary structure, comprising;

configuring an n-type epitaxial Hall element to comprise a first pair of sensing contacts disposed on a substrate layer;

surrounding said n-type epitaxial Hall element vertically by an isolation layer;

configuring a p-type Hall element to comprise a second pair of sensing contacts implanted directly on said n-type epitaxial Hall element, such that said n-type epitaxial Hall element and said p-type Hall element are biased in a parallel arrangement in order to provide a zero-bias depletion layer throughout for isolation; and

associating an insulation layer with a plurality of conductors disposed above said p-type Hall element thereby geometrically connecting said second pair of sensing contacts to geometrically corresponding said first pair of sensing contacts through a suitable resistive network and taking an output signal through said first pair of sensing contacts.

16. The method of claim 15 wherein said n-type epitaxial Hall element and said p-type Hall element comprise a pair of electrical bias contacts.

17. The method of claim 15 further comprising merging said n-type epitaxial Hall element with said p-type Hall element so that an individual stress-induced offset is associated with destructively combining the offsets of said n-type epitaxial Hall element and said p-type Hall element.

18. The method of claim 15 further comprising configuring said resistive network to restrict a variation in a magnitude of said output signal in response to temperature changes.

19. The method of claim 15 further comprising modifying said output signal to comprise a voltage signal indicative of said n-type epitaxial Hall element.

20. The method of claim 15 further comprising configuring said n-type epitaxial Hall element and said p-type Hall element on a semiconductor body comprising silicon and utilizing a silicon integrated circuit technology.