Frequency specific closed loop feedback control of integrated circuits

• US 7,626,409 B1
• Filed: 09/26/2006
• Issued: 12/01/2009
• Est. Priority Date: 04/16/2002
• Status: Expired due to Term

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Burr, James B., Koniaris, Kleanthes G.
• Primary Examiner(s): Hollington, Jermele M
• Application Number:
  US11/528,031
• Time in Patent Office: 1,162 Days
• Field of Search: None
• US Class Current: 324/760.01
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G05B 13/021 in which a variable is automatically adjusted to optimise the performance
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.

Claims

1. A method of operating an integrated circuit, said method comprising:

accessing a predetermined value of an operating characteristic of said integrated circuit, wherein said predetermined value is associated with an operating frequency of said integrated circuit;

measuring a current value of said operating characteristic of said integrated circuit; and

adjusting a plurality of controllable inputs to said integrated circuit to cause said operating characteristic of said integrated circuit to approach said predetermined value, wherein said plurality of controllable inputs comprises a body bias voltage.

2. The method of claim 1 further comprising:

periodically repeating said measuring and said adjusting.

3. The method of claim 1, wherein said plurality of controllable inputs further comprises an operating voltage of said integrated circuit.

4. The method of claim 1, wherein said body bias voltage comprises a voltage applied to an n type metal oxide semiconductor device of said integrated circuit.

5. The method of claim 1, wherein said body bias voltage comprises a voltage applied to a p type metal oxide semiconductor device of said integrated circuit.

6. The method of claim 1 further comprising:

accessing a desired operating frequency for said integrated circuit; and

determining said predetermined value based upon said desired operating frequency.

7. The method of claim 6 further comprising

storing said predetermined value in a computer usable media.

8. The method of claim 7, wherein said predetermined value is stored in a data structure that comprises multiple predetermined values, each associated with a different operating frequency.

9. The method of claim 1, wherein said operating characteristic comprises at least one characteristic selected from a group consisting of:

a temperature of said integrated circuit;

a gate delay of said integrated circuit;

an off current of said integrated circuit;

a gate leakage of said integrated circuit; and

a behavior of a device selected from a group consisting of at least one NMOS device of said integrated circuit and at least one PMOS device of said integrated circuit.

10. The method of claim 1, wherein said predetermined value is a function.

11. A system comprising:

a first circuit component configured to adjust an operating characteristic of an integrated circuit;

a second circuit component configured to provide a measured value of said operating characteristic to said first circuit component; and

wherein said first circuit component is further configured to cause said operating characteristic to approach a predetermined value in response to receiving said measured value, wherein said predetermined value is associated with an operating frequency of said integrated circuit, wherein said first circuit component is further configured to cause said operating characteristic to approach said predetermined value by adjusting a plurality of controllable inputs of said integrated circuit, and wherein said plurality of controllable inputs comprises a body bias voltage.

12. The system of claim 11 further comprising:

a computer usable media for storing said predetermined value in a data structure associated with said operating frequency.

13. The system of claim 12, wherein said data structure comprises a plurality of predetermined values, each associated with a different operating frequency.

14. The system of claim 11, wherein said plurality of controllable inputs further comprises an operating voltage of said integrated circuit.

15. The system of claim 11, wherein said body bias voltage comprises a voltage applied to an n type metal oxide semiconductor device of said integrated circuit.

16. The system of claim 11, wherein said body bias voltage comprises a voltage applied to a p type metal oxide semiconductor device of said integrated circuit.

17. The system of claim 11, wherein said operating characteristic comprises at least one characteristic selected from a group consisting of:

a temperature of said integrated circuit;

a gate delay of said integrated circuit;

an off current of said integrated circuit;

a gate leakage of said integrated circuit; and

a behavior of a device selected from a group consisting of at least one NMOS device of said integrated circuit and at least one PMOS device of said integrated circuit.