Parallel testing of semiconductor devices using a dividing voltage supply unit

• US 7,626,413 B2
• Filed: 08/04/2008
• Issued: 12/01/2009
• Est. Priority Date: 01/11/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Jung-Bae, Lee, Sang-Hoon, Ji, Joon-Su
• Primary Examiner(s): Nguyen; Vinh P
• Application Number:
  US12/185,697
• Publication Number:
  US 20080290891A1
• Time in Patent Office: 484 Days
• Field of Search: None
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Provided is a method of performing a parallel test on semiconductor devices, the method including coupling a power signal line to a set of at least two semiconductor devices through a switching device, performing at least one part of a parallel test on the set of semiconductor devices, and disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test.

Claims

1. A method of performing a parallel test, the method comprising:

testing a plurality of sets of semiconductor devices in parallel, each set including at least two semiconductor devices;

determining if at least one of the semiconductor devices of a set is defective as a result of the testing of the sets of semiconductor devices; and

disconnecting the set with at least one defective semiconductor device from at least one power signal line.

2. The method of claim 1, wherein disconnecting the set further comprises using a switching device to disconnect the set from the at least one power signal line, the switching device including a circuit module including a relay.

3. The method of claim 1, disconnecting the set further comprising disconnecting the set in response to a signal on a signal line of a performance board.

4. The method of claim 3, wherein the signal line is one selected from the group consisting of a driver signal line and an input/output signal line.

5. The method of claim 4, disconnecting the set further comprising disconnecting the set in direct response to the signal on the signal line of the performance board.

6. The method of claim 1, wherein disconnecting the set further comprises disconnecting the set with at least one defective semiconductor device even if other semiconductor devices in the set are not determined to be defective.

7. The method of claim 1, wherein each set of semiconductor devices is a set of discrete semiconductor devices, each set including a plurality of discrete semiconductor devices.