High speed level shift

• US 7,626,440 B1
• Filed: 07/04/2007
• Issued: 12/01/2009
• Est. Priority Date: 07/04/2007
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Atesoglu, Ali
• Primary Examiner(s): Zweizig; Jeffrey S
• Application Number:
  US11/825,164
• Time in Patent Office: 881 Days
• Field of Search: 326/80, 326/81, 327/318, 327/319, 327/333
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

Level shifting circuits and methods are disclosed. One embodiment provides a high speed level shifting circuit that uses an input signal to generate two intermediate signals and uses the intermediate signals to generate an output signal such that voltage stress on individual devices within the level shifting circuit is minimized. One embodiment includes a first driver and second driver coupled in parallel to provide intermediate signals to an output driver. In a particular aspect, individual transistors of the output driver are subject to voltage stresses that are less than the peak-to-peak amplitude of the output signal. In one embodiment, the first driver includes an n-channel metal oxide semiconductor (“NMOS”) cascode circuit, the second driver includes a p-channel metal oxide semiconductor (“PMOS”) cascode circuit, and the output driver includes a complementary metal oxide conductor (“CMOS”) inverter stage. In one embodiment, the level shifter is implemented in an integrated circuit characterized by 45-nanometer technology. In another embodiment, the level shifter is implemented in an integrated circuit characterized by 65-nanometer technology.

Claims

1. A level shifter comprising:

first and second drivers coupled to receive differential input signal and generate first and second differential intermediate signals from the input signal, at least one of the first and second drivers including a differential transistor pair; and

an output driver coupled to use the intermediate signals to provide differential output signal, the output signal having a greater peak-to-peak amplitude than the input signal.

2. The level shifter of claim 1 wherein the first driver includes an NMOS cascode circuit.

3. The level shifter of claim 1 wherein the first driver includes an NMOS voltage clamping circuit.

4. The level shifter of claim 1 wherein the output driver includes a cascoded inverter.

5. The level shifter of claim 1 wherein the output driver includes a voltage clamping inverter.

6. The level shifter of claim 1 wherein the output signal is a 1.8 v signal and the output driver includes thin-oxide 1.2 v transistors.

7. The level shifter of claim 1 wherein the output signal is a 1.8 v signal and all transistors included in the level shifter are thin-oxide 1.2 v transistors.

8. The level shifter of claim 1 wherein a ratio of the output signal'"'"'s voltage and a data throughput of the level shifter is substantially equal to or less than 1.8 v/10 Gbps.

9. The level shifter of claim 1 wherein the output driver includes transistors having an insulator layer thin enough such that a voltage limitation on the transistors is less than the peak-to-peak voltage amplitude of the output signal.

10. The level shifter of claim 1 wherein the first and second drivers include transistors having an insulator layer thin enough such that a voltage limitation on the transistors is less than the peak-to-peak amplitude of the output signal.

11. The level shifter of claim 1 wherein:

the first and second drivers and the output driver include transistors; and

the transistors include insulator layers of substantially similar thickness.

12. The level shifter of claim 1 wherein peak-to-peak amplitudes of the input signal, the first intermediate signal, and the second intermediate signal are substantially equal.

13. The level shifter of claim 1 wherein:

a low value of the first intermediate signal and a high value of the second intermediate signal are between a low value of the input signal and a high value of the output signal; and

the low value of the first intermediate signal is less than a high value of the second intermediate signal.

14. The level shifter of claim 1 wherein high and low values of the first intermediate signal and high and low values of the second intermediate signal span different portions of a voltage range of the output signal to facilitate minimizing voltage stress on transistors of the output driver.

15. The level shifter of claim 14 wherein the different portions of the voltage range are overlapping.

16. The level shifter of claim 1 wherein the second driver includes a PMOS cascode circuit.

17. The level shifter of claim 1 wherein the second driver includes a PMOS voltage clamping circuit.

18. The level shifter of claim 1 wherein the first driver is an NMOS stage and the second driver includes a CMOS inverter.

19. The level shifter of claim 18 further comprising a programmable current select circuit coupled to a current sink transistor of the first driver, the programmable current select circuit being programmable to select current through the first driver such that a transition time of the first intermediate signal is substantially equal to a transition time of the second intermediate signal.

20. The level shifter of claim 19 wherein the level shifter is implemented with a device technology of approximately 65 nanometers.

21. A clock data recovery circuit comprising the level shifter of claim 1.

22. A programmable logic device comprising the level shifter of claim 1.

23. A programmable logic device comprising the clock data recovery circuit of claim 21.

24. A data processing system comprising the level shifter of claim 1.

25. A level shifter comprising:

first and second drivers coupled to receive an input signal and generate first and second intermediate signals from the input signal; and

an output driver coupled to use the intermediate signals to provide an output signal, the output signal having a greater peak-to-peak amplitude than the input signal wherein;

the first driver is an NMOS stage;

the first driver includes resistors and a current sink transistor;

the current sink transistor is coupled to a bias voltage; and

a resistance of the resistors and a value of the bias voltage are selected to control current and voltages in the first driver such that a low value of the first intermediate signal is greater than a low value of the input signal.

26. The level shifter of claim 25 wherein:

the second driver is a PMOS stage;

the second driver further includes resistors and a current source transistor;

the current source transistor is coupled to a bias voltage; and

a resistance of the resistors and a value of the bias voltage are selected to control current and voltages in the second driver such that a high value of the second intermediate signal is less than a level of a source voltage powering the second driver.

27. A level shifter comprising:

first and second drivers coupled to receive an input signal and generate first and second intermediate signals from the input signal; and

an output driver coupled to use the intermediate signals to provide an output signal, the output signal having a greater peak-to-peak amplitude than the input signal where;

the second driver is a PMOS stage;

the second driver further includes resistors and a current source transistor;

the current source transistor is coupled to a bias voltage; and

a resistance of the resistors and a value of the bias voltage are selected to control current and voltages in the second driver such that a high value of the second intermediate signal is less than a level of a source voltage powering the second driver.

28. The level shifter of claim 27 wherein the level shifter is implemented with a device technology of approximately 45 nanometers.

29. A method of shifting a level of an electronic signal comprising:

receiving differential input signal having an input low value and an input high value;

using the input signal to generate first and second differential intermediate signals, the first intermediate signal having a first intermediate low value and a first intermediate high value and the second intermediate signal having a second intermediate low value and a second intermediate high value; and

using the first and second intermediate signals to generate an differential output signal, the output signal having an output low value and an output high value, a peak-to-peak amplitude of the output signal being greater than a peak-to-peak amplitude of the input signal.

30. The method of claim 29 wherein peak-to-peak amplitudes of the input signal, the first intermediate signal, and the second intermediate signal are substantially equal.

31. The method of claim 29 wherein:

the first intermediate low value and the second intermediate high values are between the input low value and the output high value;

the first intermediate low value is less than the second intermediate high value; and

the second intermediate high value is less than the first intermediate high value.

32. The method of claim 29 wherein high and low values of the first and second intermediate signals span different portions of a voltage range of the output signal to facilitate minimizing voltage stress on transistors of the output driver.

33. The method of claim 32 wherein the different portions of the voltage range are overlapping.

34. A level shifter comprising:

means for using a differential input signal to generate first and second differential intermediate signals; and

means for using the first and second intermediate signals to generate aft differential output signal wherein;

the output signal has a greater peak-to-peak amplitude than the input signal; and

voltage ranges of the first and second intermediate signals each include different portions of a voltage range of the output signal.

35. The level shifter of claim 34 wherein the different portions are overlapping.

36. The level shifter of claim 34 wherein peak-to-peak amplitudes of the input signal and the first and second intermediate signals are substantially equal.

37. The level shifter of claim 34 further comprising means for controlling a transition time of the first intermediate signal to substantially match a transition time of the second intermediate signal.