Low latency multi-level communication interface

• US 7,626,442 B2
• Filed: 03/03/2006
• Issued: 12/01/2009
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos, Zerbe, Jared L., Werner, Carl W., Chau, Pak S., Garlepp, Bruno W., Horowitz, Mark A., Donnelly, Kevin S., Garrett, Billy W. Jr.
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/368,012
• Publication Number:
  US 20060170453A1
• Time in Patent Office: 1,369 Days
• Field of Search: 327/336, 327/34, 327/374, 375/286, 375/287, 375/317, 375/340, 375/264, 375/353
• US Class Current: 327/336
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Claims

1. A multi-mode PAM output driver for driving a symbol, the output driver comprising:

logic circuitry; and

a driver circuit coupled to the logic circuitry and configured to drive the symbol;

wherein the multi-mode PAM output driver is capable of operating in a specified mode of a plurality of predefined modes;

wherein the symbol is an N-PAM symbol when the specified mode is a first mode;

wherein the symbol is an M-PAM symbol when the specified mode is a second mode; and

wherein N is not equal to M.

2. The multi-mode PAM output driver of claim 1, wherein N is equal to 2.

3. The multi-mode PAM output driver of claim 1, wherein N is equal to 2 and M is equal to 4.

4. The multi-mode PAM output driver of claim 1, wherein M and N are both integers selected from the group consisting of 2, 4, 8, and 16.

5. The multi-mode PAM output driver of claim 1, wherein the output driver drives the symbol onto a multi-drop bus.

6. The multi-mode PAM output driver of claim 1,

wherein the logic circuitry is configured to receive data;

wherein, when the specified mode is a first mode, the driver circuit outputs signals representing the received data, the signals including one or more N-PAM modulated symbols; and

wherein, when the specified mode is a second mode, the driver circuit outputs signals representing the received data, the signals including one or more M-PAM modulated symbols.

7. The multi-mode PAM output driver of claim 6, wherein, when the specified mode is a second mode, the received data comprises at least two bits including a most significant bit (MSB) and a least significant bit (LSB).

8. The multi-mode PAM output driver of claim 6, wherein the received data represents at least part of an address in a memory system.

9. The multi-mode PAM output driver of claim 6, wherein the received data represents at least part of a value stored in a memory system.

10. The multi-mode PAM output driver of claim 6, wherein the received data represents at least part of a command in a memory system.

11. The multi-mode PAM output driver of claim 1,

wherein, when the specified mode is a first mode, the driver circuit drives a sequence of symbols representing received data at a first symbol rate, the sequence of symbols including one or more N-PAM modulated symbols;

wherein, when the specified mode is a second mode, the driver circuit drives a sequence of symbols representing the received data at a second symbol rate, the sequence of symbols including one or more M-PAM modulated symbols; and

wherein the first symbol rate is not equal to the second symbol rate.

12. The multi-mode PAM output driver of claim 11, wherein the first symbol rate is twice the second symbol rate.

13. The multi-mode PAM output driver of claim 11, wherein the ratio between the second symbol rate and the first symbol rate is equal to log₂(N)/log₂(M).

14. A method of data transmission, comprising:

configuring an multi-mode PAM output driver to operate in a specified mode of a plurality of predefined modes;

receiving data at the multi-mode PAM output driver;

using the multi-mode PAM output driver, outputting a symbol corresponding to at least a portion of the received data;

wherein the symbol is an N-PAM symbol when a specified mode is a first mode;

wherein the symbol is an M-PAM symbol when the specified mode is a second mode; and

wherein N is not equal to M.

15. The method of claim 14, wherein M and N are both integers selected from the group consisting of 2, 4, 8, and 16.

16. The method of claim 14, the method further including:

operating the multi-mode PAM output driver so as to drive a sequence of symbols onto a first signal path at a predetermined symbol rate, the sequence comprising a plurality of symbols, each symbol having a respective level of a predetermined number of PAM levels;

receiving, at a multi-mode PAM receiver, the sequence of symbols from a second signal path;

determining, based on a relationship between the sequence of driven symbols and the sequence of received symbols, an error metric; and

when the error metric is greater than an error metric threshold,

decreasing the symbol rate, the number of PAM levels, or both, and

subsequently repeating the operating the multi-mode PAM output driver,

receiving at the multi-mode PAM receiver, and determining the error metric.

17. The method of claim 16, wherein the multi-mode PAM output driver and multi-mode PAM receiver are embodied on a single integrated circuit.

18. The method of claim 16, wherein the first signal path and second signal path comprise the same physical medium.

19. The method of claim 18, wherein the signal path is a multi-drop bus.

20. The method of claim 16, wherein the operating the multi-mode PAM output driver, receiving at the multi-mode PAM receiver, and determining the error metric are performed periodically at a rate defined by a predetermined interval of time.

21. The method of claim 16, wherein the symbol rate is initially one of a plurality of available symbol rates and the number of PAM levels is initially one of a plurality of available numbers of PAM levels, the method further comprising:

when the error metric is less than or equal to the error metric threshold and either

the symbol rate is not the maximum symbol rate in the plurality of symbol rates, or

the number of PAM levels is not the maximum number of PAM levels in the plurality of numbers of PAM levels,

increasing the symbol rate, the number of PAM levels, or both, and

subsequently repeating the operating the multi-mode PAM output driver,

receiving at the multi-mode PAM receiver, and determining the error metric.

22. The method of claim 21, wherein the symbol rate is determined by selecting the symbol rate from amongst the plurality of available symbol rates, the plurality of available rates including a first symbol rate and a second symbol rate, wherein the second symbol rate is twice the first symbol rate.

23. The method of claim 21, wherein the symbol rate is determined by selecting the symbol rate from amongst the plurality of available symbol rates, the plurality of available rates including a first symbol rate and a second symbol rate, wherein the ratio between the second symbol rate and the first symbol rate is equal to log₂(N)/log₂(M).

24. The method of claim 14, the method further including;

operating the multi-mode PAM output driver so as to drive a first sequence of symbols at a first symbol rate selected from a plurality of predetermined symbol rates, the sequence comprising a plurality of symbols, each symbol having a respective level of a first number of PAM levels, the first number of PAM levels selected from a plurality of available PAM levels;

receiving at a multi-mode PAM receiver the first sequence of symbols;

determining, based on voltage and timing characteristics of the first sequence of received symbols, a first set of signal characteristics, the set of signal characteristics corresponding to the first symbol rate and to the first number of PAM levels;

operating the multi-mode PAM driver so as to drive a second sequence of symbols at a second symbol rate selected from the plurality of predetermined symbol rates, the sequence comprising a plurality of symbols, each symbol having a respective level of a second number of PAM levels, the second number of PAM levels selected from the plurality of available PAM levels;

receiving at a multi-mode PAM receiver the second sequence of symbols;

determining, based on voltage and timing characteristics of the second sequence of received symbols, a second set of signal characteristics, the set corresponding to the second symbol rate and to the second level of predetermined number of PAM levels;

based on the first and the second set of characteristics, choosing a mode of operation of the system, the mode of operation specified, at least, by a symbol rate and a number of PAM levels.