Automatic frequency compensation for pulse width modulated RF level control

• US 7,626,463 B2
• Filed: 08/24/2007
• Issued: 12/01/2009
• Est. Priority Date: 08/25/2006
• Status: Active Grant

• Current Assignee: Ambrell Corporation (inTEST Corporation)
• Original Assignee: Ameritherm, Inc. (inTEST Corporation)
• Inventors: Paull, Ian Alan
• Primary Examiner(s): Chang; Joseph
• Assistant Examiner(s): Tan; Richard
• Application Number:
  US11/844,789
• Publication Number:
  US 20080048789A1
• Time in Patent Office: 830 Days
• Field of Search: 331/16, 323/282, 323/283, 323/288, 363/41
• US Class Current: 331/16
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H05B 6/06 Control, e.g. of temperature, of power

Abstract

Preferred embodiments of the present invention provide systems and methods that automatically correct the desired on-time of switching elements as the resonant frequency changes, so as to maintain the correct proportional value.

Claims

1. A system for automatically allocating to switching devices an on-time that is proportional to a cycle time, comprising:

a voltage controlled oscillator configured to receive a tune voltage and configured to output a first signal having a frequency that corresponds to the tune voltage;

a charge accumulating circuit;

a voltage controlled current source configured to receive the tune voltage or a scaled tune voltage and configured to charge the charge accumulating circuit by outputting a current that corresponds to the received tune voltage or the received scaled tune voltage;

a comparator configured to generate a second signal by comparing a voltage of the charge accumulating circuit to a pre-determined set point; and

a circuit configured to receive the first signal and the second signal and configured to output a third signal that is a function of the first signal and the second signal,

wherein the output of said circuit is coupled to the switching devices.

2. The system of claim 1, further comprising:

an edge detector circuit; and

a reset circuit,

wherein the edge detector circuit and the reset circuit are configured to discharge the charge accumulating circuit at the beginning of each cycle of said first signal.

3. The system of claim 1, further comprising an analog voltage scaling circuit configured to receive the tune voltage and configured to output to the current source a scaled tune voltage.

4. The system of claim 1, wherein the comparator is configured to output a first voltage in response to the comparator determining that the voltage of the charge accumulating circuit is less than a pre-determined set point, and is configured to output a second voltage in response to the comparator determining that the voltage of the charge accumulating circuit is greater than a pre-determined set point.

5. The system of claim 1, wherein the circuit comprises a logical circuit that implements an AND function.

6. The system of claim 1, wherein the charge accumulating circuit consists of a capacitor.

7. The system of claim 1, wherein the charge accumulating circuit comprises one or more capacitors.

8. A method for automatically allocating to switching devices an on-time that is proportional to a cycle time, comprising:

producing a tune voltage;

producing a first signal having a frequency that is dependent on the tune voltage;

charging a charge accumulating circuit using the tune voltage or a scaled tune voltage;

producing a second signal, wherein the step of producing the second signal comprises comparing a voltage of the charge accumulating circuit to a pre-determined set point;

using the second signal to gate the first signal to the switching devices.

9. The method of claim 8, further comprising discharging the charge accumulating circuit at the beginning of each cycle of said first signal.

10. The method of claim 8, further comprising using a scaling circuit to produce said scaled tune voltage.

11. The method of claim 8, wherein the step of producing the second signal further comprises:

outputting a first voltage if the voltage of the charge accumulating circuit is less than a pre-determined set point; and

outputting a second voltage if the voltage of the charge accumulating circuit is greater than the pre-determined set point.

12. The method of claim 8, wherein the step of using the second signal to gate the first signal to the switching devices comprises:

ANDing the first signal with the second signal to produce a third signal; and

using the third signal to drive the switching devices.

13. The method of claim 8, wherein the charge accumulating circuit consists of a capacitor.

14. The method of claim 8, wherein the charge accumulating circuit comprises one or more capacitors.