Systems, methods, and apparatus for indicating faults within a power circuit utilizing dynamically modified inrush restraint

• US 7,626,794 B2
• Filed: 10/16/2006
• Issued: 12/01/2009
• Est. Priority Date: 10/18/2005
• Status: Active Grant

• Current Assignee: Schweitzer Engineering Laboratories, Incorporated
• Original Assignee: Schweitzer Engineering Laboratories, Incorporated
• Inventors: Swartzendruber, Ryan W., Feight, Laurence V., Salewske, Tyson J.
• Primary Examiner(s): Jackson; Stephen W
• Application Number:
  US11/582,256
• Publication Number:
  US 20070086140A1
• Time in Patent Office: 1,142 Days
• Field of Search: 361/93.1
• US Class Current: 361/93.1
• CPC Class Codes: G01R 19/16547 voltage or current in AC supplies switching for protection H02H; circuits for emergency power supply H02J9/00

Abstract

A faulted circuit indicator comprises a processor, which dynamically determines a conductor de-energization level based on a monitored average current. This dynamically-determined de-energization level and/or monitored average current may be used to provide dynamic inrush restraint and/or dynamic backfeed restraint (reset restraint). If current within a power conductor falls below the determined de-energization level, the processor determines that the conductor has de-energized, and accordingly ignores high current spikes less than a predetermined duration that occur during re-energization.

Claims

1. A faulted circuit indicator for detecting abnormally high current levels on a power conductor comprising:

i) a housing;

ii) a current acquisition circuit disposed within said housing and adapted to monitor current within said power conductor;

iii) an averaging circuit for generating an average current, said averaging circuit disposed within said housing and coupled to said current acquisition circuit; and

iv) a processor coupled to said current acquisition circuit and said averaging circuit, said processor generating a de-energization level based on said average current and ignoring abnormally high current levels on said power conductor for a predetermined time after said monitored current rises above said de-energization level.

2. The faulted circuit indicator of claim 1, wherein said processor determines a trip level based on said average current and wherein said de-energization level is set to a mathematical function related to said trip level.

3. The faulted circuit indicator of claim 2, wherein said de-energization level is set to 5% of said trip level.

4. A method for detecting abnormally high current levels as a result of inductive load inrush on a power conductor comprising the steps of:

i) monitoring a current level within said power conductor;

ii) determining an average current;

iii) generating a de-energization level based on said average current; and

iv) ignoring abnormally high current levels on said power conductor for a predetermined time after said monitored current rises above said de-energization level.

5. The method of claim 4, further comprising the step of generating a trip level based on said average current, and wherein said de-energization level is set to a fraction of said trip level.

6. The method of claim 5, wherein the de-energization level is set to 5% of said trip level.

7. A faulted circuit indicator for detecting abnormally high current levels on a power conductor comprising:

i) means for monitoring a current level within said power conductor;

ii) means for determining an average current;

iii) means for generating a de-energization level based on said average current; and

iv) means for ignoring abnormally high current levels on said power conductor for a predetermined time after said monitored current rises above said de-energization level.

8. The faulted circuit indicator of claim 7, further comprising means for generating a trip level, and wherein said de-energization level is set to a fraction of said trip level.

9. The faulted circuit indicator of claim 8, wherein said de-energization level is set to 5% of said trip level.