Adaptive voltage control for SRAM
First Claim
1. A system configured to set an operating voltage of an SRAM memory device, comprising:
- an SRAM memory array;
a test structure configured to characterize one or more parameters predictive of a functionality of the SRAM memory array; and
a controller configured to set at least one operating voltage for the SRAM memory array based at least in part on the characterization of the parameters.
1 Assignment
0 Petitions
Accused Products
Abstract
The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage.
29 Citations
46 Claims
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1. A system configured to set an operating voltage of an SRAM memory device, comprising:
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an SRAM memory array; a test structure configured to characterize one or more parameters predictive of a functionality of the SRAM memory array; and a controller configured to set at least one operating voltage for the SRAM memory array based at least in part on the characterization of the parameters. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for setting an operating voltage for an SRAM memory device based on test structure characteristics of one or more parameters that predict a functionality of an SRAM array, comprising:
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operating the test structure and reading the characteristics of the test structure; and setting an operating voltage for the SRAM array based at least in part on the characteristics and a correlation with the functionality that satisfies one or more predetermined yield criteria of the SRAM array. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A system configured to set an operating voltage of an SRAM memory device, comprising:
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an SRAM memory array comprising an SRAM memory cell; a test structure configured to characterize one or more parameters predictive of a functionality of the SRAM memory array, wherein the functionality of the SRAM array comprises a static noise margin (SNM); and a controller configured to set the operating voltage for the SRAM memory array based on the characterization of the one or more parameters. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37)
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38. A system configured to set an array operating voltage and a peripheral circuit operating voltage of an SRAM memory device, comprising:
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an SRAM memory array comprising an SRAM memory cell; SRAM peripheral circuitry; a test structure configured to characterize one or more parameters predictive of a functionality of the SRAM memory array; and a controller configured to set the array operating voltage for the SRAM memory array and the peripheral circuit operating voltage for the SRAM peripheral circuitry based on the characterization of the one or more parameters. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46)
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Specification