Method and apparatus for transmitting data with reduced coupling noise

• US 7,627,043 B2
• Filed: 05/17/2005
• Issued: 12/01/2009
• Est. Priority Date: 06/14/2000
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark A., Perino, Donald V.
• Primary Examiner(s): PHU, PHUONG M
• Application Number:
  US11/130,502
• Publication Number:
  US 20050208838A1
• Time in Patent Office: 1,659 Days
• Field of Search: 375/257, 375/285, 375/346, 327/565, 326/38, 326/41, 326/101, 439/941, 370/201
• US Class Current: 375/257
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating

Abstract

A first integrated circuit is coupled to a first connector. A second connector is coupled to the first connector through multiple conductors, in which alternating pairs of conductors are reversed. A second integrated circuit is coupled to the second connector through a second group of conductors. The first integrated circuit includes multiple differential drivers and the second integrated circuit includes multiple differential receivers. The inductive coupling coefficient of the first device is modified to be substantially the same as the inductive coupling coefficient of the second device.

Claims

1. A system comprising:

a printed circuit board;

a first integrated circuit mounted on the printed circuit board, where the first integrated circuit comprises a plurality of differential drivers;

a second integrated circuit mounted on the printed circuit board, where the second integrated circuit comprises a plurality of differential receivers;

a plurality of pairs of conductors each electrically coupling a respective one of the differential drivers to a respective one of the differential receivers, wherein each alternating pair of the plurality of pairs of conductors includes a first conductor crossover where a first conductor of that alternating conductor pair is crossed over a second conductor of that alternating conductor pair, and for each alternating pair of conductors that includes a first conductor crossover, further comprising;

(i) a second conductor crossover where the second conductor of that alternating conductor pair is crossed over the first conductor of that alternating conductor pair;

or

(ii) coupling that alternating pair to a differential receiver having inputs with an orientation that is reversed to that of an adjacent differential receiver, and wherein each of the other pairs of conductors, besides said alternating pairs, does not include any crossover.

2. The system of claim 1, wherein the first integrated circuit has a first inductive coupling coefficient and the second integrated circuit has a second inductive coupling coefficient that is substantially the same as the first inductive coupling coefficient.

3. The system of claim 1, wherein the first integrated circuit and the second integrated circuit are memory devices.

4. The system of claim 1, wherein the printed circuit board is a module.

5. The system of claim 4, wherein the printed circuit board is a memory module.

6. The system of claim 1, further comprising at least one connector electrically coupled to the plurality of pairs of conductors, wherein the at least one connector is situated between the first integrated circuit and the second integrated circuit.

7. The system of claim 6, wherein the first conductor crossover is between the at least one connector and at least one of the first integrated circuit and the second integrated circuit.

8. The system of claim 1, further comprising two connectors electrically coupled to the plurality of pairs of conductors, wherein the two connectors are situated between the first integrated circuit and the second integrated circuit.

9. The system of claim 8, wherein the first conductor crossover is between the two connectors.

10. A system comprising:

a printed circuit board;

a first integrated circuit mounted on the printed circuit board, where the first integrated circuit comprises a plurality of differential drivers;

a second integrated circuit mounted on the printed circuit board, where the second integrated circuit comprises a plurality of differential receivers;

a plurality of conducting line pairs each electrically coupling a respective one of the differential drivers to a respective one of the differential receivers, wherein each alternating line pair of the plurality of conducting line pairs has a reversed polarity at one end thereof that is electrically coupled to a differential driver or receiver having inputs with an orientation that is reversed to that of an adjacent differential driver or receiver, respectively.

11. The system of claim 10, wherein each alternating line pair comprises a first line crossed over a second line.

12. The system of claim 10, wherein the first integrated circuit has a first inductive coupling coefficient and the second integrated circuit has a second inductive coupling coefficient that is substantially the same as the first inductive coupling coefficient.

13. The system of claim 10, wherein the first integrated circuit and the second integrated circuit are memory devices.

14. The system of claim 10, wherein the printed circuit board is a module.

15. The system of claim 10, further comprising at least one connector electrically coupled to the plurality of conducting line pairs between the first integrated circuit and the second integrated circuit, wherein lines of each alternating line pair cross over one another between the at least one connector and at least one of the first integrated circuit and the second integrated circuit.

16. The system of claim 10, further comprising two connectors electrically coupled to the plurality of conducting line pairs between the first integrated circuit and the second integrated circuit, wherein lines of each alternating line pair cross over one another between the two connectors.

17. A system comprising:

a printed circuit board including at least a first line pair, a second line pair disposed adjacent the first line pair, and a third line pair disposed adjacent to the second line pair;

a first integrated circuit disposed on the printed circuit board, wherein the first integrated circuit is coupled to the first line pair, second line pair and third line pair;

a second integrated circuit disposed on the printed circuit board and electrically coupled to the first line pair, second line pair, and third line pair, wherein each of the first line pair and third line pair includes a first crossover where a first line of each of the first and third line pairs is crossed over a second line of each of the first and third line pairs, respectively, and a second crossover where the second line of each of the first and third line pairs is crossed over the first line of each of the first and third line pairs, respectively, and wherein the second line pair does not include any crossover.

18. The system of claim 17, wherein the first integrated circuit has a first inductive coupling coefficient and the second integrated circuit has a second inductive coupling coefficient that is substantially the same as the first inductive coupling coefficient.

19. The system of claim 17, wherein the first integrated circuit and the second integrated circuit are memory devices.

20. The system of claim 17, wherein the system is a module.

21. The system of claim 17, wherein the system is a memory module.

22. The system of claim 17, further comprising at least one connector electrically coupled to the plurality of conducting line pairs between the first integrated circuit and the second integrated circuit, wherein each of the first and third line pairs comprises a first line crossed over a second line between the at least one connector and at least one of the first integrated circuit and the second integrated circuit.

23. The system of claim 17, further comprising two connectors electrically coupled to the first line pair, second line pair and third line pair between the first integrated circuit and the second integrated circuit.

24. The system of claim 17, wherein:

the first integrated circuit comprises a differential driver coupled to the first line pair; and

the second integrated circuit comprises a differential receiver coupled to the first line pair.

25. A system comprising:

a first line pair, a second line pair disposed adjacent the first line pair, and a third line pair disposed adjacent to the second line pair;

a first integrated circuit including a first differential driver coupled to the first line pair, a second differential driver coupled to the second line pair, and a third differential driver coupled to the third line pair; and

a second integrated circuit including a first differential receiver coupled to the first line pair, a second differential receiver coupled to the second line pair, and a third differential receiver coupled to the third line pair, wherein each of the first line pair and third line pair includes a first line crossed over a second line, wherein the first differential receiver and the third differential receiver have inputs with an orientation that is reversed to that of the second differential receiver.

26. The system of claim 25, wherein the first integrated circuit and the second integrated circuit are memory devices.

27. A module comprising:

a first integrated circuit;

a second integrated circuit; and

a plurality of pairs of conductors electrically coupling the first integrated circuit to the second integrated circuit, wherein each alternating pair of the plurality of pairs of conductors includes a first crossover having a first line crossed over a second line, and a second crossover having the second line crossed back over the first line, and wherein each of the other pairs of conductors, besides said alternating pairs, does not include any crossover.

28. The system of claim 27, wherein the first integrated circuit and the second integrated circuit are memory devices.

29. The system of claim 27, wherein the first integrated circuit and the second integrated circuit each comprise a plurality of differential drivers and a plurality of differential receivers, wherein each differential driver of the plurality of differential drivers is coupled to a respective pair of conductors of the plurality of pairs of conductors and wherein each differential receiver of the plurality of differential receivers is coupled to a respective pair of conductors of the plurality of pairs of conductors.

30. A memory module comprising:

a first integrated circuit memory device, where the first integrated circuit comprises a plurality of differential drivers;

a second integrated circuit memory device, where the second integrated circuit comprises a plurality of differential receivers;

a plurality of pairs of conductors each electrically coupling a respective one of the differential drivers to a respective one of the differential receivers, wherein each alternating pair of the plurality of pairs of conductors includes a first line crossed over a second line; and

an inverter coupled to the output of each differential receiver that is coupled to an alternating pair of the plurality of pairs of conductors, and wherein each of the other pairs of conductors, besides said alternating pairs, does not include any crossover.

31. The system of claim 30, wherein the first integrated circuit memory device comprises a plurality of differential drivers, wherein each differential driver of the plurality of differential drivers is coupled to a respective pair of conductors of the plurality of pairs of conductors.

32. The system of claim 30, wherein each differential receiver of the plurality of differential receivers is coupled to the respective pair of conductors of the plurality of pairs of conductors.