Clock-edge modulated serial link with DC-balance control
DC CAFCFirst Claim
Patent Images
1. A signal transmitter, comprising:
- a channel node to interface with a single direct current balanced differential channel; and
circuitry connected to the channel node, the circuitry being configured to multiplex clock, data and control signals and apply them to the channel node, wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals.
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Abstract
A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
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Citations
19 Claims
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1. A signal transmitter, comprising:
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a channel node to interface with a single direct current balanced differential channel; and circuitry connected to the channel node, the circuitry being configured to multiplex clock, data and control signals and apply them to the channel node, wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A signal receiver, comprising:
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a channel node to interface with a channel configured as a single direct current balanced differential channel; and circuitry connected to the channel node, the circuitry configured to de-multiplex clock, data and control signals from the channel node, wherein the circuitry identifies direct current balancing control signals within a pulse width modulated clock signal. - View Dependent Claims (9, 10, 11, 12)
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13. A battery powered computing device, comprising:
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a channel configured as a single direct current balanced differential channel; a signal transmitter connected to the channel, the signal transmitter being configured to multiplex clock, data, and control signals, wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals, the signal transmitter configured to apply the multiplexed signals to the channel; and a signal receiver connected to the channel, the signal receiver configured to de-multiplex the clock, data and control signals from the channel node, the signal receiver configured to identify and recover the direct current balancing control signals from the pulse width modulated clock signal. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification