Expanded memory for communications controller
First Claim
1. A communication system comprising:
- a communications controller configured to control transmission and reception of communications data in a network, wherein the communications controller comprises a timer having a preset corresponding to an estimated time of completion of at least one of the burst read data transfer and the burst write data transfer;
a first memory configured to store configuration data associated with the communications controller and application parameters associated with each of a plurality of communications applications; and
an interface converter interconnecting the communications controller and the first memory and configured to convert a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read and write data transfer of the configuration data and the application parameters between the communications controller and the first memory, wherein the read and write data transfer comprises a burst read data transfer and a burst write data transfer of a plurality of consecutive data blocks associated with the configuration data and application parameters between the communications controller and the first memory via the interface converter and wherein the communications controller is further configured to write a predefined data pattern in an end address of consecutive address registers in an address space associated with the one of the communications controller and the first memory to which the plurality of consecutive data blocks are transferred.
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Abstract
One embodiment of the present invention includes a communication system. The system comprises a communications controller configured to control transmission and reception of communications data in a network. The system also comprises a memory configured to store configuration data associated with the communications controller and application parameters associated with each of a plurality of communications applications. The system further comprises an interface converter interconnecting the communications controller and the memory and configured to convert a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read and write data transfer of the configuration data and the application parameters between the communications controller and the memory.
22 Citations
14 Claims
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1. A communication system comprising:
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a communications controller configured to control transmission and reception of communications data in a network, wherein the communications controller comprises a timer having a preset corresponding to an estimated time of completion of at least one of the burst read data transfer and the burst write data transfer; a first memory configured to store configuration data associated with the communications controller and application parameters associated with each of a plurality of communications applications; and an interface converter interconnecting the communications controller and the first memory and configured to convert a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read and write data transfer of the configuration data and the application parameters between the communications controller and the first memory, wherein the read and write data transfer comprises a burst read data transfer and a burst write data transfer of a plurality of consecutive data blocks associated with the configuration data and application parameters between the communications controller and the first memory via the interface converter and wherein the communications controller is further configured to write a predefined data pattern in an end address of consecutive address registers in an address space associated with the one of the communications controller and the first memory to which the plurality of consecutive data blocks are transferred. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for communicating with a memory device, the method comprising:
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transmitting a plurality of consecutive data blocks from a communications controller on a first data bus via inter-integrated circuit (I2C) protocol; converting the I2C protocol to a second bus interface protocol for transmission of the plurality of consecutive data blocks on a second data bus; storing the plurality of consecutive data blocks in the memory device via the second data bus; writing a predefined data pattern at an end address register of a plurality of address registers in the memory device; setting a preset time associated with a timer corresponding to an estimated time of completion of the transmission of the plurality of consecutive data blocks from the communications controller; incrementing the timer; and monitoring the end address register in the memory device upon the timer reaching the preset time to indicate a completion of the transmission of the plurality of consecutive data blocks from the communications controller. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A communication system comprising:
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means for controlling transmission and reception of communications data in a network, comprising; means for initiating the read data transfer as a burst read data transfer and the write data transfer as a burst write data, such that each of the configuration data and the application parameters are configured as a plurality of consecutive data blocks that are sequentially transmitted between the means for controlling and the means for storing; means for completing the burst read data transfer and the burst write data transfer based on one of a means for generating an interrupt signal; means for writing a predefined data pattern into an end address register of a plurality of consecutive address registers; means for storing configuration data associated with the means for controlling and for storing application parameters associated with each of a plurality of communications applications; and means for converting a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read data transfer of the configuration data and the application parameters from the means for storing to the means for controlling and write data transfer of the application parameters from the means for controlling to the means for storing; means for timing the burst read data transfer and the burst write data transfer, comprising means for determining the presence of the predefined data pattern upon completion of a time associated with one of the burst read data transfer and the burst write data transfer.
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Specification