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Modular processor debug core connection for programmable chip systems

  • US 7,627,784 B1
  • Filed: 04/06/2005
  • Issued: 12/01/2009
  • Est. Priority Date: 04/06/2005
  • Status: Active Grant
First Claim
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1. A method for implementing a programmable chip, comprising:

  • providing a processor core for implementation on the programmable chip, the processor core having a debug port;

    selecting a debug core associated with the processor core, the debug core operable to allow control and monitoring of the processor core;

    connecting the debug core to the debug port associated with the processor core;

    implementing the debug core and the processor core on the programmable chip,wherein the debug core is associated with a debug core interface allowing access to a plurality of debug core submodules; and

    wherein the plurality of debug core submodules are selected from a library of debug core submodules comprising a control submodule and a trigger submodule.

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