Modular processor debug core connection for programmable chip systems

• US 7,627,784 B1
• Filed: 04/06/2005
• Issued: 12/01/2009
• Est. Priority Date: 04/06/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Atsatt, Sean R., Allen, Timothy P., Ball, James Loran
• Primary Examiner(s): Lohn; Joshua A
• Application Number:
  US11/101,027
• Time in Patent Office: 1,700 Days
• Field of Search: 714/30, 714/31, 710/110, 710/100
• US Class Current: 714/30
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3648 using additional hardware
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

Methods and apparatus are provided for implementing a semiconductor device with a debug core separate from a processor core. The user configurable debug core can be customized to include one or more debug core submodules. Each debug core submodule is generally associated with a particular debug feature such as trace generation, performance counters, or hardware triggers. The debug core can be driven through a variety of interfaces to allow debugging, monitoring, and control of processor operations.

Claims

1. A method for implementing a programmable chip, comprising:

providing a processor core for implementation on the programmable chip, the processor core having a debug port;

selecting a debug core associated with the processor core, the debug core operable to allow control and monitoring of the processor core;

connecting the debug core to the debug port associated with the processor core;

implementing the debug core and the processor core on the programmable chip,

wherein the debug core is associated with a debug core interface allowing access to a plurality of debug core submodules; and

wherein the plurality of debug core submodules are selected from a library of debug core submodules comprising a control submodule and a trigger submodule.

2. The method of claim 1, wherein the debug core comprises an Intellectual Property (IP) block.

3. The method of claim 1, wherein the plurality of debug core submodules includes a monitor memory.

4. The method of claim 3, wherein the monitor memory stores instructions and data associated with the processor core.

5. The method of claim 1, wherein the control submodule is configured to break, single-step, and reset the processor core.

6. The method of claim 1, wherein the plurality of debug core submodules includes a performance counter submodule.

7. The method of claim 6, wherein the performance counter submodule measures the performance of processor core events.

8. The method of claim 1, wherein the plurality of debug core submodules includes a trace compression submodule.

9. The method of claim 8, wherein the trace compression submodule creates a stream of compressed trace information.

10. The method of claim 1, wherein the plurality of debug core submodules includes an off-chip trace submodule.

11. The method of claim 10, wherein the off-chip trace submodule sends compressed trace information to an external trace storage device.

12. The method of claim 1, wherein the debug core is coupled to the processor core using multiple master component interconnection fabric.

13. The method of claim 1, wherein the debug core is accessed using a Joint Test Action Group (JTAG) interface.

14. A programmable chip, comprising:

a processor core including a debug interface; and

a debug core having a plurality of debug core submodules, the debug core coupled to the processor core and configured to control and monitor the processor core through the debug interface, the debug core associated with a debug core interface allowing access to the plurality of debug core submodules; and

wherein the plurality of debug core submodules are selected from a library of debug core submodules comprising a control submodule and a trigger submodule.

15. The programmable chip of claim 14, wherein the debug core comprises an Intellectual Property (IP) block.

16. The programmable chip of claim 14, wherein the plurality of debug core submodules includes a monitor memory, wherein the monitor memory stores instructions and data associated with the processor core.

17. The programmable chip of claim 14, wherein the plurality of debug core submodules includes a control submodule, wherein the control submodule is configured to break, single-step, and reset the processor core.

18. The programmable chip of claim 14, wherein the plurality of debug core submodules includes a trigger submodule.

19. The programmable chip of claim 14, wherein the plurality of debug core submodules includes a performance counter submodule, wherein the performance counter submodule measures the performance of processor core events.

20. The programmable chip of claim 14, wherein the plurality of debug core submodules includes a trace compression submodule, wherein the trace compressions submodule creates a stream of compressed trace information.

21. The programmable chip of claim 14, wherein the plurality of debug core submodules includes an off-chip trace submodule, wherein the off-chip trace submodule sends compressed trace information to an external trace storage device.

22. The programmable chip of claim 14, wherein the debug core is coupled to the processor core using multiple master component interconnection fabric.

23. The programmable chip of claim 14, wherein the debug core is accessed using a Joint Test Action Group (JTAG) interface.

24. A computer readable medium comprising computer code embodied therein, the computer code for implementing a programmable chip, the computer readable medium comprising:

computer code for selecting a debug core associated with a processor core for implementation on the programmable chip, the processor core having a debug port, the debug core operable to allow control and monitoring of the processor core, said debug core comprising a plurality of debug core submodules;

computer code for connecting between the debug core and the debug port associated with the processor core; and

computer code for implementing the debug core and the processor core on the programmable chip;

wherein the plurality of debug core submodules are selected from a library of debug core submodules comprising a control submodule and a trigger submodule.

25. A method comprising:

selecting a processor core for implementation on a programmable chip, the processor core including a debug port;

selecting a debug core and one or more debug core submodules from a library, the debug core associated with the processor core and operable to control and monitor the processor core, said a library of debug core submodules comprising a control submodule and a trace compression submodule;

generating a hardware description language file, the hardware description language file describing a design including the processor core, the debug core, and interconnections; and

,

implementing the design on the programmable chip.