Automated integrated circuit development

• US 7,627,838 B2
• Filed: 04/25/2006
• Issued: 12/01/2009
• Est. Priority Date: 04/25/2006
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Keswick, Paul D.
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Memula, Suresh
• Application Number:
  US11/411,258
• Publication Number:
  US 20070250800A1
• Time in Patent Office: 1,316 Days
• Field of Search: 716 16- 18, 716 2- 3
• US Class Current: 716/132
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/396 Clock trees

Abstract

Customization methodology for integrated circuit (e.g., clocks) design customization using a software tool that integrates multiple integrated circuit development operations.

Claims

1. A computer-implemented method, comprising:

receiving a customer specification for a custom integrated circuit at a processing device, wherein the customer specification comprises one or more integrated circuit parameters, wherein the one or more integrated circuit parameters comprises a package input parameter and a package output parameter; and

developing the custom integrated circuit based on the customer specification using a software tool which integrates a plurality of integrated circuit development operations, wherein the software tool operates on the processing device, wherein the plurality of integrated circuit development operations comprises front end operations and back end operations, the method further comprising performing the front end operations by the software tool while operating at a customer site, and wherein the front end operations comprises;

selecting a package for the custom integrated circuit based on the package input parameter;

selecting a pin layout for the selected package;

selecting a base die for the custom integrated circuit based on the package output parameter, wherein the base die comprises components and circuitry to perform electronic functions;

selecting a pad assignment for the selected base die, wherein the pad assignment comprises a plurality of bonding pads that make electrical connection to a plurality of package pins of the package; and

generating an initial pin-to-pad mapping of the electrical connections between the plurality of bonding pads and the plurality of package pins of the package.

2. The method of claim 1, wherein the custom integrated circuit comprises a clock circuit.

3. The method of claim 1, wherein developing the custom integrated circuit comprises selecting one of a plurality of predetermined functions of the custom integrated circuit by altering integrated circuit design data corresponding to a metal mask layer used to fabricate the custom integrated circuit.

4. The method of claim 3, wherein the integrated circuit design data comprises a netlist.

5. The method of claim 1, wherein developing the custom integrated circuit comprises customizing a standard integrated circuit design to generate the custom integrated circuit by altering integrated circuit design data corresponding to a metal mask layer used to fabricate the custom integrated circuit.

6. The method of claim 5, wherein the integrated circuit design data comprises a netlist.

7. The method of claim 6, wherein the netlist is expressed as a graphical design system II (GDSII) file.

8. The method of claim 1, further comprising fabricating a commercial unit of the custom integrated circuit, wherein one of the plurality of integrated circuit development operations comprises generation of a datasheet specification, wherein the commercial unit matches the datasheet specification.

9. The method of claim 1, further comprising performing the back end operations at a site other than the customer site.

10. The method of claim 1, wherein the initial pin-to-pad mapping is an bonding diagram which graphically represents the electrical connections between the plurality of bonding pads and the plurality of package pins of the package.

11. The method of claim 1 wherein the front end operation further comprise:

generating a datasheet for the custom integrated circuit; and

generating an input/output (I/O) buffer information specification (IBIS) model.

12. A computer-implemented method, comprising:

receiving a customer specification for a custom integrated circuit at a processing device, wherein the customer specification comprises one or more integrated circuit parameters, wherein the one or more integrated circuit parameters comprises a package input parameter and a package output parameter; and

developing the custom integrated circuit based on the customer specification using a software tool which integrates a plurality of integrated circuit development operations, wherein the software tool operates on the processing device, wherein the plurality of integrated circuit development operations comprises front end operations and back enc operations, the method further comprising performing the front end operations by the software tool while operating at a customer site, and wherein the front end operations comprises selecting a base die for the custom integrated circuit based on the package output parameter, wherein the base die comprises components and circuitry to perform electronic functions.

13. The method of claim 12, wherein the front end operations further comprise generating a datasheet for the custom integrated circuit.