Method for making a micromechanical device by using a sacrificial substrate

• US 7,629,190 B2
• Filed: 03/29/2005
• Issued: 12/08/2009
• Est. Priority Date: 03/15/2001
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Patel, Satyadev R., Huibers, Andrew G.
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US11/094,086
• Publication Number:
  US 20050170546A1
• Time in Patent Office: 1,715 Days
• Field of Search: 257414-416, 257/E29.324, 359/120, 438/106, 438 48- 50
• US Class Current: 438/48
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00214 Processes for the simultaneaous manufacturing of a network or an array of similar microstructural devices
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 1/00896 Temporary protection during separation into individual elements
• CPC Class Codes: B81C 1/00904 Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01054 : Xenon [Xe]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method is disclosed for forming a micromechanical device. The method includes fully or partially forming one or more micromechanical structures multiple times on a first substrate. A second substrate is bonded onto the first substrate so as to cover the multiple areas each having one or more micromechanical structures, so as to form a substrate assembly. The substrate assembly is then separated into individual dies, each die having the one or more micromechanical structures held on a portion of the first substrate, with a portion of the second substrate bonded to the first substrate portion. Finally, the second substrate portion is removed from each die to expose the one or more micromechanical structures on the first substrate portion. The invention is also directed to a method for forming a micromechanical device, including: forming one or more micromechanical structures in one or more areas on a first substrate; bonding caps onto the first substrate so as to cover the one or more areas each having one or more micromechanical structures, so as to form a substrate assembly; after a period of time, removing the caps to expose the one or more micromechanical structures. During the period of time between bonding the caps and later removing the caps, the substrate assembly can be singulated, inspected, irradiated, annealed, die attached, shipped and/or stored.

Claims

1. A method for making a micromirror device, the method comprising:

forming circuitry, electrodes and micromirrors in a plurality of die areas on a silicon wafer;

bonding a light transmissive sealing wafer in spaced apart relation to the silicon wafer;

after the bonding, singulating the bonded wafers into individual dies; and

removing the light transmissive sealing wafer from the silicon wafer.

2. The method of claim 1, further comprising providing an anti-stiction layer on the micromirrors.

3. The method of claim 1, wherein the singulation of the bonded wafers comprises scoring and breaking the bonded wafers into individual dies.

4. The method of claim 1, wherein the singulation comprises separating the light transmissive sealing wafer and the silicon wafer such that after singulation an edge of a silicon substrate of an individual die is offset from an edge of a light transmissive substrate of an individual die leaving an exposed area on the silicon substrate.

5. The method of claim 4, wherein the bonding comprises application of an adhesive and a spacer.

6. The method of claim 5, wherein the adhesive is an epoxy.

7. The method of claim 5, wherein the separation is performed by sawing with pressurized water.

8. The method of claim 1, wherein the light transmissive sealing wafer is a glass wafer.

9. The method of claim 8, wherein the glass sealing wafer is display grade glass.

10. The method of claim 8, wherein the micromirrors on each die are at least 1000 mirrors.

11. The method of claim 10, wherein between 1 and 6 million mirrors are provided on each die.

12. The method of claim 11, wherein each die area is rectangular.

13. The method of claim 4, further comprising after singulation electrically testing each die at the exposed area of the silicon substrate of the die.

14. The method of claim 13, further comprising discarding dies that fail the electrical testing.

15. The method of claim 13, wherein testing of the dies further comprises optically testing each die after singulation.

16. The method of claim 8, further comprising attaching each die into a package.

17. The method of claim 1, further comprising attaching a plurality of dies onto a single packaging substrate.

18. The method of claim 17, wherein the packaging substrate is a ceramic substrate.

19. The method of claim 1, further comprising attaching each die after wafer singulation to a packaging substrate.

20. The method of claim 19, further comprising wirebonding each die to the packaging substrate.

21. The method of claim 17, further comprising wirebonding the plurality of dies to the packaging substrate, followed by singulating the packaging substrate.

22. The method of claim 1, wherein the plurality of dies are attached and wirebonded to a bottom packaging substrate, and wherein an electrical probe contacts the bottom packaging substrate for testing each die.

23. The method of claim 1, wherein a plurality of dies after singulation are attached to a panel having precision formed gaps that allow for precision X and Y alignment for kinematic mounting in a projection system.

24. The method of claim 1, wherein the silicon substrate for each die after singulation is bonded to a kinematic mounting package.

25. The method of claim 1, further comprising contacting an electrical testing probe to an exposed I/O pad area for testing purposes.

26. The method of claim 4, wherein the exposed area on the silicon substrate of each die is an I/O pad area.

27. The method of claim 26, further comprising connecting to the I/O pad area an external display controller that supports mirroring a displayed image in a horizontal axis and/or vertical axis.

28. The method of claim 25, wherein testing further comprises actuating the micromirrors.

29. The method of claim 28, wherein the testing further comprises viewing movement of the micromirrors optically.

30. The method of claim 28, wherein a camera is used to image capture movement of the micromirrors.

31. The method of claim 30, wherein the camera is a CCD camera.

32. The method of claim 28, wherein each micromirror is actuated individually for optical testing.

33. The method of claim 28, wherein groups of micromirrors are actuated for optical testing.

34. The method of claim 28, wherein a distance of movement of a micromirror is determined for an applied voltage.

35. The method of claim 28, further comprising optical testing prior to singulation of the wafers into dies.

36. The method of claim 1, further comprising providing an intermediate wafer with open areas between the silicon wafer and light transmissive sealing wafer to maintain the silicon wafer and light transmissive wafer in spaced apart relation.

37. The method of claim 1, further comprising forming spacers on the light transmissive sealing wafer prior to bonding the light transmissive sealing wafer to the silicon wafer.

38. The method of claim 1, further comprising an intermediate mirror substrate wherein the micromirrors are etched or cut out of the intermediate mirror substrate.

39. The method of claim 19, further comprising providing the packaged die within a projection system.

40. The method of claim 38, wherein the intermediate mirror substrate is bonded to the silicon wafer and the silicon wafer is further bonded to the light transmissive sealing wafer.

41. The method of claim 38, wherein the intermediate mirror substrate is bonded to the silicon wafer and wherein the intermediate mirror substrate is bonded to the light transmissive sealing wafer.

42. The method of claim 38, wherein the mirrors in the intermediate mirror substrate are formed by a deep RIE silicon etch.

43. The method of claim 42, further comprising a reflecting layer deposited on the intermediate mirror substrate.

44. The method of claim 38, wherein the micromirrors are formed by an RIE etch.

45. The method of claim 43, wherein the reflecting layer is deposited after forming the micromirrors from the intermediate substrate.

46. The method of claim 43, wherein the reflecting layer is deposited before forming the micromirrors from the intermediate substrate.