Patterning self-aligned transistors using back surface illumination

• US 7,629,206 B2
• Filed: 02/26/2007
• Issued: 12/08/2009
• Est. Priority Date: 02/26/2007
• Status: Expired due to Fees

• Current Assignee: 3M Innovative Properties Company (3M Company), Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: 3M Innovative Properties Company (3M Company), Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Haase, Michael Albert, Street, Robert A.
• Primary Examiner(s): Nhu; David
• Application Number:
  US11/710,880
• Publication Number:
  US 20080206914A1
• Time in Patent Office: 1,016 Days
• Field of Search: 438/149, 438/151, 438/159, 438/158, 438/308, 438/712, 438/723, 438/742
• US Class Current: 438/149
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Fabrication methods for making thin film devices on transparent substrates are described. Gate, source, and drain electrodes of a transistor are formed on a transparent substrate. The widths of the drain electrode and source electrodes are greater than a width of the gate electrode. A dielectric layer is formed on the gate electrode. A semiconductor layer is deposited proximate to the gate, source and drain electrodes. Photoresist is deposited on the semiconductor. The photoresist is exposed to light directed through the transparent substrate so that the gate electrode masks the photoresist from the light. The semiconductor layer is removed in regions exposed to the light.

Claims

1. A method of patterning a semiconductor layer to form a display backplane, comprising:

forming gate, source, and drain electrodes of a transistor on a transparent substrate having a first surface and a second surface, a width of the drain electrode and a width of the source electrode greater than a width of the gate electrode, wherein forming the source and drain electrodes comprises forming data lines and pixel electrodes of the display backplane and forming the gate electrodes comprises forming enable lines of the display backplane;

depositing a semiconductor layer comprising ZnO or a-Si;

H proximate to the gate, source and drain electrodes;

depositing photoresist over the semiconductor layer;

exposing the photoresist through a mask to light directed toward the first surface of the transparent substrate;

exposing the photoresist to light directed through the second surface of the transparent substrate, the gate electrode masking the photoresist from the light; and

removing the semiconductor layer in regions exposed to the light.

2. The method of patterning a semiconductor layer according to claim 1, wherein:

forming the gate electrode comprises forming the gate electrode on the first surface of the transparent substrate; and

depositing the semiconductor layer comprises depositing the semiconductor layer over the gate electrode.

3. The method of patterning a semiconductor layer according to claim 1, wherein the width of the drain and source electrodes and the width of the gate electrode accommodates misregistration of the gate electrodes with at least one of the drain and source electrodes.

4. The method of patterning a semiconductor layer according to claim 1, wherein an alignment tolerance of the mask relative to the gate electrodes is about +/−

100 microns.

5. The method of patterning a semiconductor layer according to claim 1, wherein the width of at least one of the drain and source electrodes is greater than about three times the width of the gate electrodes.

6. The method of patterning a semiconductor layer according to claim 1, wherein the transparent substrate comprises a flexible substrate.

7. The method of patterning a semiconductor layer according to claim 1, wherein the transparent substrate comprises a polymer.

8. A method of fabricating a display backplane, comprising:

forming enable lines of the display backplane on a transparent substrate having a first surface and a second surface, the enable lines comprising gate electrodes of transistors;

forming an array of pixel electrodes and data lines on the transparent substrate, the array of pixel electrodes forming columns of pixel electrodes, each pixel electrode including an electrode extension oriented substantially orthogonal to the enable lines, the electrode extensions forming source or drain electrode of the transistors;

depositing a semiconductor layer proximate to the enable lines, the pixel electrodes, and the data lines;

depositing photoresist over the semiconductor layer;

exposing the photoresist through a mask to light directed toward the first surface of the transparent substrate;

exposing the photoresist to light directed through the second surface of the transparent substrate, the enable lines masking the photoresist from the light; and

removing the semiconductor layer in regions where the photoresist was exposed to the light.

9. The method of fabricating a display backplane according to claim 8, wherein each electrode extension extends in a direction of a column along an edge of a next pixel electrode in the column.

10. The method of fabricating a display backplane according to claim 8, further comprising selecting a length of the electrode extensions to achieve a desired alignment tolerance between backplane layers.

11. The method of fabricating a display backplane according to claim 8 wherein alignment of the enable lines and the pixel electrodes varies across the backplane, the variation in alignment related to substrate distortion during fabrication.

12. The method of fabricating a display backplane according to claim 8, further comprising distorting the transparent substrate during fabrication, the distortion causing misalignment of the enable lines and the electrode extensions.

13. The method of fabricating a display backplane according to claim 8, further comprising forming storage capacitors where the enable lines cross the pixel electrodes.

14. A method of fabricating a display backplane, comprising:

patterning enable lines and data lines on a transparent substrate having a first surface and a second surface, the width of the data lines being greater than about three times the width of the enable lines;

forming a semiconductor layer over the enable lines;

depositing photoresist over the semiconductor layer;

exposing the photoresist through a mask to light directed toward the first surface of the transparent substrate;

exposing the photoresist to light through the second surface of the transparent substrate; and

removing the semiconductor layer in regions exposed to the light.

15. The method of fabricating a display backplane according to claim 14, wherein the transparent substrate is flexible.