Trench MOSFET with terraced gate and manufacturing method thereof

• US 7,629,646 B2
• Filed: 05/16/2007
• Issued: 12/08/2009
• Est. Priority Date: 08/16/2006
• Status: Expired due to Fees

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hshieh, Fwu-Iuan
• Primary Examiner(s): Tran; Minh-Loan T
• Assistant Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US11/749,463
• Publication Number:
  US 20080042194A1
• Time in Patent Office: 937 Days
• Field of Search: None
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the sidewalls and bottoms of the trenches. A polysilicon layer is filled in the trenches, wherein the polysilicon layer is higher than the sidewalls of the trenches to be used as a gate of the MOSFET. A plurality of sources and bodies are formed in the epitaxial layer, and the bodies at both sides of the trenches. An insulating layer is covered on the substrate, wherein a plurality of metal contact windows are provided. Metal plugs are filled in the metal contact windows to form metal connections for the MOSFET.

Claims

1. A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced gate, comprising:

a substrate;

an epitaxial layer disposed on the substrate;

a plurality of trenches each defined by at least a sidewall and a bottom formed on top of the epitaxial layer;

a gate oxide layer formed on the sidewall and the bottom of each trench;

a polysilicon layer disposed in the trenches, wherein the polysilicon layer protrudes out from each of the trenches and at least a portion of the polysilicon layer is positioned higher than the sidewall of each of the trenches;

a plurality of source regions and body regions formed in the epitaxial layer such that the polysilicon layer that is disposed in the trenches surrounded by the source regions is configured to conduct current of the MOSFET;

an insulating layer deposited on the epitaxial layer,

a plurality of metal contact holes formed in the insulating layer and extending through the insulating layer, the source regions and into the body regions vertically relative to a surface of the epitaxial layer for contacting respective source and body regions for source metal connection;

a plurality of metal contact holes formed in the insulating layer and extending through the insulating layer and into the polysilicon layer in the trenches for gate metal connection; and

metal plugs disposed in the metal contact holes to form the source metal connection and the gate metal connections for the MOSFET.

2. The MOSFET of claim 1, wherein the metal contact holes in the polysilicon layer for the gate metal connection avoids polysilicon seam regions in the middle of the polysilicon layer.

3. The MOSFET of claim 1, wherein the metal plugs connected to the metal contact holes for the source metal connection are made of tungsten metal materials surrounded by barrier metals along both a sidewall and a bottom of each of the metal contact holes for connecting the respect source and body regions.

4. The transistor of claim 1, wherein the gate oxide layer in trench gates is single oxide of which oxide thickness nearly uniform along trench sidewall and bottom.

5. The transistor of claim 1, wherein the gate oxide layer at the bottoms of trench gates has a significant larger thickness than trench sidewall so as to reduce the capacitance of the gate oxide layer.