Voltage level shifter

• US 7,629,830 B1
• Filed: 07/30/2008
• Issued: 12/08/2009
• Est. Priority Date: 07/30/2008
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rubin, Adam
• Primary Examiner(s): Le; Dinh T.
• Application Number:
  US12/182,478
• Time in Patent Office: 496 Days
• Field of Search: 326 62- 63, 326 80- 81, 327/306, 327/333, 327/24
• US Class Current: 327/333
• CPC Class Codes: H03K 3/021 by the use, as active elements, of more than one type of element or means, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration

Abstract

A voltage level shifter circuit, comprising diodes to provide a voltage buffer to reduce output voltage swings, and edge detection circuits to momentarily turn on pull-up pMOSFETs so as to speed up the voltage level shifting at input signal transitions and to mitigate static power dissipation. Other embodiments are described and claimed.

Claims

1. A circuit comprising:

a first input port having a first input voltage;

a low-side rail and a low-side power rail;

a first pull-down transistor comprising a gate coupled to the first input port, a source connected to the low-side rail, and a drain;

a first pull-up transistor comprising a source connected to the drain of the first pull-down transistor, a drain connected to the low-side power rail, and a gate;

a first edge detection circuit for receiving said first input signal to provide a voltage pulse to the gate of the first pull-up transistor in response to a falling edge in the first input voltage; and

a first diode connected between an output port and the source of the first pull-up transistor.

2. The circuit as set forth in claim 1, the first diode comprising a transistor comprising a base connected to the source of the first pull-up transistor, a collector connected to the low-side rail, and an emitter.

3. The circuit as set forth in claim 2, further comprising:

the output port connected to the emitter of the first diode.

4. The circuit as set forth in claim 1, further comprising:

a high-side transistor comprising a gate, a drain connected to the first diode, and a source; and

a high-side power rail connected to the source of the high-side transistor.

5. The circuit as set forth in claim 1, further comprising:

a second input port having a second input voltage;

a second pull-down transistor comprising a gate coupled to the second input port, a source connected to the low-side rail, and a drain;

a second pull-up transistor comprising a source connected to the drain of the second pull-down transistor, a drain connected to the low-side power rail, and a gate;

a second edge detection circuit to provide a voltage pulse to the gate of the second pull-up transistor in response to a falling edge in the second input voltage; and

a second diode connected to the source of the second pull-up transistor.

6. The circuit as set forth in claim 5,

the first diode comprising a transistor comprising a base connected to the source of the first pull-up transistor, a collector connected to the low-side rail, and an emitter;

and

the second diode comprising a transistor comprising a base connected to the source of the second pull-up transistor, a collector connected to the low-side rail, and an emitter.

7. The circuit as set forth in claim 6, further comprising:

a first output port connected to the emitter of the first diode; and

a second output port connected to the emitter of the second diode.

8. The circuit as set forth in claim 5, further comprising:

a first high-side transistor comprising a gate connected to the second diode, a drain connected to the first diode, and a source;

a second high-side transistor comprising a gate connected to the first diode, a drain connected to the second diode, and a source; and

a high-side power rail connected to the source of the first high-side transistor and to the source of the second high-side transistor.

9. A computer system comprising:

a memory module;

a processor comprising a memory controller; and

an interface circuit coupled to the memory controller and the memory module, the interface circuit comprising;

a first input port having a first input voltage;

a low-side rail and a low-side power rail;

a first pull-down transistor comprising a gate coupled to the first input port, a source connected to the low-side rail, and a drain;

a first pull-up transistor comprising a source connected to the drain of the first pull-down transistor, a drain connected to the low-side power rail, and a gate;

a first edge detection circuit for receiving said first input signal to provide a voltage pulse to the gate of the first pull-up transistor in response to a falling edge in the first input voltage; and

a first diode connected between a first output port and the source of the first pull-up transistor.

10. The computer system as set forth in claim 9, the interface circuit further comprising:

a second input port having a second input voltage;

a second pull-down transistor comprising a gate coupled to the second input port, a source connected to the low-side rail, and a drain;

a second pull-up transistor comprising a source connected to the drain of the second pull-down transistor, a drain connected to the low-side power rail, and a gate;

a second edge detection circuit to provide a voltage pulse to the gate of the second pull-up transistor in response to a falling edge in the second input voltage; and

a second diode connected to the source of the second pull-up transistor.

11. The computer system as set forth in claim 10, the interface circuit further comprising:

a first high-side transistor comprising a gate connected to the second diode, a drain connected to the first diode, and a source;

a second high-side transistor comprising a gate connected to the first diode, a drain connected to the second diode, and a source; and

a high-side power rail connected to the source of the first high-side transistor and to the source of the second high-side transistor.

12. The computer system as set forth in claim 11,

the first diode comprising a transistor comprising a base connected to the source of the first pull-up transistor, a collector connected to the low-side rail, and an emitter;

and

the second diode comprising a transistor comprising a base connected to the source of the second pull-up transistor, a collector connected to the low-side rail, and an emitter.

13. The computer system as set forth in claim 12, the interface circuit further comprising:

the first output port connected to the emitter of the first diode; and

a second output port connected to the emitter of the second diode.

14. The computer system as set forth in claim 9,

the first diode comprising a transistor comprising a base connected to the source of the first pull-up transistor, a collector connected to the low-side rail, and an emitter;

and

the second diode comprising a transistor comprising a base connected to the source of the second pull-up transistor, a collector connected to the low-side rail, and an emitter.

15. The computer system as set forth in claim 9, the interface circuit further comprising:

a first output port connected to the emitter of the first diode; and

the second output port connected to the emitter of the second diode.