Voltage level shifter
First Claim
Patent Images
1. A circuit comprising:
- a first input port having a first input voltage;
a low-side rail and a low-side power rail;
a first pull-down transistor comprising a gate coupled to the first input port, a source connected to the low-side rail, and a drain;
a first pull-up transistor comprising a source connected to the drain of the first pull-down transistor, a drain connected to the low-side power rail, and a gate;
a first edge detection circuit for receiving said first input signal to provide a voltage pulse to the gate of the first pull-up transistor in response to a falling edge in the first input voltage; and
a first diode connected between an output port and the source of the first pull-up transistor.
1 Assignment
0 Petitions
Accused Products
Abstract
A voltage level shifter circuit, comprising diodes to provide a voltage buffer to reduce output voltage swings, and edge detection circuits to momentarily turn on pull-up pMOSFETs so as to speed up the voltage level shifting at input signal transitions and to mitigate static power dissipation. Other embodiments are described and claimed.
-
Citations
15 Claims
-
1. A circuit comprising:
-
a first input port having a first input voltage; a low-side rail and a low-side power rail; a first pull-down transistor comprising a gate coupled to the first input port, a source connected to the low-side rail, and a drain; a first pull-up transistor comprising a source connected to the drain of the first pull-down transistor, a drain connected to the low-side power rail, and a gate; a first edge detection circuit for receiving said first input signal to provide a voltage pulse to the gate of the first pull-up transistor in response to a falling edge in the first input voltage; and a first diode connected between an output port and the source of the first pull-up transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A computer system comprising:
-
a memory module; a processor comprising a memory controller; and an interface circuit coupled to the memory controller and the memory module, the interface circuit comprising; a first input port having a first input voltage; a low-side rail and a low-side power rail; a first pull-down transistor comprising a gate coupled to the first input port, a source connected to the low-side rail, and a drain; a first pull-up transistor comprising a source connected to the drain of the first pull-down transistor, a drain connected to the low-side power rail, and a gate; a first edge detection circuit for receiving said first input signal to provide a voltage pulse to the gate of the first pull-up transistor in response to a falling edge in the first input voltage; and a first diode connected between a first output port and the source of the first pull-up transistor. - View Dependent Claims (10, 11, 12, 13, 14, 15)
-
Specification