Delay stage, ring oscillator, PLL-circuit and method

• US 7,629,856 B2
• Filed: 10/27/2006
• Issued: 12/08/2009
• Est. Priority Date: 10/27/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Thaller, Edwin
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): Gannon; Levi
• Application Number:
  US11/588,877
• Publication Number:
  US 20080111638A1
• Time in Patent Office: 1,138 Days
• Field of Search: 331/57, 331/45, 327/149, 327/153, 327/158, 327/161, 327/266, 327/274, 327/277, 327/280, 327/284, 327/287
• US Class Current: 331/57
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45236 Two dif amps realised in MOS or JFET technology, one of them being of the p-channel type and the other one of the n-channel type, are coupled in parallel with their gates
• CPC Class Codes: H03F 2203/45318 the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled
• CPC Class Codes: H03F 2203/45352 the AAC comprising a combination of a plurality of transistors, e.g. Darlington coupled transistors
• CPC Class Codes: H03F 2203/45366 the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45652 the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 2005/00215 where the conduction path of multiple FET's is in parallel or in series, all having the same gate control
• CPC Class Codes: H03K 2005/00228 having complementary input and output signals
• CPC Class Codes: H03K 2005/0028 using varicaps, e.g. gate capacity of a FET with specially defined threshold, as delaying capacitors
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

A delay stage for a semiconductor device includes at least one delay branch and at least one controllable switching apparatus. The at least one controllable switching apparatus is configured to connect a predefined amount of the at least one delay branch to a supply voltage.

Claims

1. A delay stage for a semiconductor device, comprising:

at least two pairs of complimentary delay branches in parallel, each pair of complimentary delay branches comprising at least one inverter, a first branch and a second branch; and

at least one controllable switching apparatus, wherein an arbitrary amount of the at least two pairs of complimentary delay branches is connectable to a supply voltage to provide different frequency ranges depending on the amount of parallel connected delay branches.

2. The delay stage as claimed in claim 1, wherein the controllable switching apparatus has at least two different control signals, each of the different control signals connecting to different pairs of the complimentary delay branches, to activate or deactivate the different pairs of the complimentary delay branches to provide different frequency ranges depending on the amount of parallel connected delay branches.

3. The delay stage as claimed in claim 1, further comprising at least one output terminal configured to provide corresponding output signals having an output frequency set up by the controllable switching apparatus.

4. The delay stage as claimed in claim 1, wherein the controllable switching apparatus comprises controllable switches configured to connect the delay branches in parallel to each other.

5. The delay stage as claimed in claim 1, wherein the controllable switching apparatus comprises controllable switches configured to connect at least two pairs of complimentary delay branches to the supply voltage.

6. The delay stage as claimed in claim 1, further comprising at least one control terminal to receive at least one control signal, wherein the at least one control terminal is connected to corresponding control terminals of the controllable switching apparatus.

7. The delay stage as claimed in claim 1, further comprising an input terminal configured to receive an input signal.

8. The delay stage as claimed in claim 1, further comprising a first supply terminal configured to receive a first supply potential and a second supply terminal configured to receive a second supply potential wherein the second supply potential is lower than the first supply potential and wherein the supply voltage is derived from the first and the second supply potential.

9. The delay stage as claimed in claim 8, wherein the first supply potential is a positive supply potential and the second supply potential is a negative supply potential.

10. The delay stage as claimed in claim 1, wherein within at least a first of the delay branches is connectable to the first supply terminal via a first controllable switch, and is further connectable to the second supply terminal via a second controllable switch, wherein when the first and second controllable switches are switched off the first delay branch is disconnected from the supply voltage and when the first and second controllable switches are switched on the first delay branch is connected to the supply voltage.

11. The delay stage as claimed in claim 10, wherein the first and second controllable switches include semiconductor switches.

12. The delay stage as claimed in claim 10, wherein the first and second controllable switches include CMOS-based transistors.

13. The delay stage as claimed in claim 10, wherein the first and second controllable switches include digital switches designed to connect or disconnect a corresponding delay branch digitally by applying a digital control signal to their control terminals.

14. The delay stage as claimed in claim 1, wherein at least a first of the at least one inverters is connected to an input terminal to receive an input signal, wherein the first inverter is connected via the controllable switching apparatus to the supply voltage and wherein the first inverter is connected to an output terminal to provide the output signal.

15. The delay stage as claimed in claim 1, wherein each of the inverters are connected to a common input terminal and a common output terminal.

16. The delay stage as claimed in claim 1, wherein each of the inverters comprises a low output impedance and wherein each of the inverters is designed to load and unload a capacitive load of a further delay stage connectable downstream to an output terminal of the delay stage.

17. The delay stage as claimed in claim 1, wherein the delay stage is a differential delay stage.

18. The delay stage as claimed in claim 17, wherein the differential delay stage comprises two complementary input terminals to receive complementary input signals and two complementary output terminals to provide complementary output signals.

19. The delay stage as claimed in claim 17, wherein each one of the first and second branch within a pair of complementary delay branches comprises an inverter.

20. The delay stage as claimed in claim 17, wherein a positive feedback circuit is provided which is arranged between the first and second branches of the two pairs of complementary delay branches and which provides a positive feedback signal for each one of the first and second branch to support the oscillation.

21. The delay stage as claimed in claim 20, wherein the positive feedback circuit comprises two transistors having control terminals and output terminals that, the control terminals and output terminals of the two transistors cross-coupled.

22. A ring oscillator circuit, comprising:

a first delay stage; and

at least one second delay stage coupled to the first delay stage,

wherein at least one of the first and second delay stages comprising at least two pairs of complimentary delay branches in parallel, wherein each of the at least two pairs of complimentary delay branches includes at least one inverter and each pair of complimentary delay branches comprising a first branch and a second branch, and at least one controllable switching apparatus, wherein an arbitrary amount of the at least pairs of complimentary delay branches is connectable to a supply voltage to provide different frequency ranges depending on the amount of parallel connected delay branches.

23. The ring oscillator as claimed in claim 22, wherein the controllable switching apparatus has at least two different control signals, each of the different control signals connecting to different pairs of the complimentary delay branches, to activate or deactivate the different pairs of the complimentary delay branches to provide different frequency ranges depending on the amount of parallel connected delay branches.

24. The ring oscillator as claimed in claim 22, wherein the switching apparatus comprises controllable switches to connect the delay branches within the at least one first and second delay stages in parallel to each other.

25. The ring oscillator as claimed in claim 22, wherein the switching apparatus comprises controllable switches to connect the at least two pairs of complimentary delay branches within the at least one first and second delay stages to the supply voltage.

26. The ring oscillator as claimed in claim 22, further comprising an oscillator output terminal for providing an oscillator output signal having an oscillator frequency set up by the first and second delay stages.

27. The ring oscillator as claimed in claim 22, wherein each one of the delay stages comprises at least one input terminal and at least one output terminal, wherein the output terminals of the second delay stage are connected to the input terminals of the first delay stage and wherein the input terminals of the second delay stage are connected to the output terminals of the first delay stage.

28. The ring oscillator as claimed in claim 22, further comprising a supply voltage tuning circuit configured to tune at least one of the first or the second supply potentials.

29. The ring oscillator as claimed in claim 22, further comprising a start-up tuning circuit to tune the oscillator to the maximum oscillation frequency.

30. The ring oscillator as claimed in claim 22, further comprising at least one frequency divider, which is arranged in series connection with respect to the output terminal of the second delay stage.

31. The ring oscillator as claimed in claim 30, wherein the frequency dividers are designed to operate at the highest possible frequency of the oscillator.

32. The ring oscillator as claimed in claim 30, wherein the frequency dividers are designed to operate at the highest actual programmed frequency of the oscillator.

33. The ring oscillator as claimed in claim 22, wherein the oscillator is a voltage controlled oscillator.

34. A PLL-circuit, comprising:

an oscillator wherein the oscillator comprises a first delay stage and at least one second delay stage coupled to the first delay stage, wherein at least one of the first and second delay stages comprising at least one controllable switching apparatus and at least two pairs of complimentary delay branches in parallel wherein each of the at least two pairs of complimentary delay branches includes at least one inverter, and further wherein an arbitrary amount of the at least two pairs of complimentary delay branches of the corresponding delay stage is connectable to a supply voltage to provide different frequency ranges depending on the amount of parallel connected delay branches.

35. The PLL-circuit as claimed in claim 34, wherein the oscillator is a ring oscillator.

36. The PLL-circuit as claimed in claim 34, further comprising a first input terminal to receive an input signal, an output terminal to provide an output signal and a second input terminal to receive a second input signal derived from the output signal.

37. The PLL-circuit as claimed in claim 34, further comprising a phase detector and a loop filter wherein the phase detector, the loop filter and the oscillator are arranged one after the other and between the input terminals and the output terminal.

38. The PLL-circuit as claimed in claim 34, wherein the phase detector is a phase frequency detector.

39. The PLL-circuit as claimed in claim 34, wherein the phase detector is designed to generate a phase difference signal, which indicates the phase difference between the first and the second input signals.

40. The PLL-circuit as claimed in claim 34, wherein the loop filter is a digital loop filter.

41. The PLL-circuit as claimed in claim 39, wherein the loop filter comprises a low-pass filter to filter the phase difference signal and to provide a filtered phase difference voltage signal.

42. The PLL-circuit as claimed in claim 41, wherein the oscillator is controlled by the filtered phase difference voltage signal and the oscillator then generates the output signal of the PLL-circuit wherein the output signal has the predefined frequency range.

43. A method for operating a delay stage for a semiconductor device, comprising:

providing at least one controllable switching apparatus and at least two pairs of complimentary delay branches in parallel, wherein each of the at least two pairs of complimentary delay branches includes at least one inverter; and

switching at least one switch by providing corresponding control signals to corresponding control terminals of the corresponding switches to connect an arbitrary amount of the at least two pairs of complimentary delay branches of the corresponding delay stage to a supply voltage to provide different frequency ranges depending on the amount of parallel connected delay branches.

44. The method as claimed in claim 43, wherein the controllable switching apparatus has at least two different control signals, each of the different control signals connecting to different pairs of the complimentary delay branches, to activate or deactivate the different pairs of the complimentary delay branches to provide different frequency ranges depending on the amount of parallel connected delay branches.

45. The method as claimed in claim 43, wherein an output frequency of an output signal of the delay stage is set up by switching the at least one switch.

46. The method as claimed in claim 43, wherein an output frequency of an output signal of the delay stage is set up by switching the at least one switch of a switched capacitor network able switch to connect at least one capacitor to an output terminal of the delay stage.

47. A method for operating a ring oscillator circuit, comprising:

providing a first delay stage and at least one second delay stage coupled to the first delay stage, wherein at least one of the first and second delay stages comprising at least two pairs of complimentary delay branches, wherein each of the at least two pairs of complimentary delay branches includes at least one inverter, and at least one switching apparatus; and

switching at least one switch of the switching apparatus by providing corresponding control signals to corresponding control terminals of the corresponding switches to connect an arbitrary amount of the at least two pairs of complimentary delay branches to a supply voltage.

48. The ring oscillator as claimed in claim 47, wherein the predefined amount of delay branches are connected in parallel to each other.

49. The method as claimed in claim 47, wherein at least one supply potential is tuned.

50. The method as claimed in claim 47, wherein the oscillator is tuned to a maximum oscillation frequency.

51. The method as claimed in claim 47, wherein the oscillator is designed to operate at a highest possible frequency.

52. The method as claimed in claim 47, wherein the oscillator operates at a highest actual programmed frequency.