Semiconductor memory device and method for erasing the same
First Claim
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1. A semiconductor memory device comprising:
- a memory cell array with NAND cell units arranged therein, the NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit to a bit line and a source line, respectively, and dummy cells disposed between the select gate transistors and the memory cells neighbored to them,wherein the dummy cells are set in a threshold voltage distribution higher than the erased threshold voltage of the memory cell by combination of a first program state and a second program state, the first program state being for boosting the threshold voltage of the dummy cells with a program voltage applied while the second program state being for suppressing an increase of the threshold voltage of the dummy cells in comparison with the first program state after reaching a certain threshold level,wherein the dummy cell is programmed in the first program state with the program voltage applied thereto under the condition that a first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the first program state, andwherein the dummy cell is programmed in the second program state with the program voltage applied thereto under the condition that a second bit line control voltage higher than the first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the second program state.
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Abstract
A semiconductor memory device includes NAND cell units each having memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit and dummy cells disposed between the select gate transistors and the memory cells neighbored to them. The dummy cells are set in a threshold voltage distribution higher than the erased threshold voltage of the memory cell by combination of a first program mode and a second program mode, the first program mode being for boosting the threshold voltage of the dummy cells with a program voltage applied while the second program mode is for boosting the threshold voltage of the dummy cells after reaching a certain threshold level under the condition that the threshold voltage increase is suppressed in comparison with the first program mode.
48 Citations
15 Claims
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1. A semiconductor memory device comprising:
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a memory cell array with NAND cell units arranged therein, the NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit to a bit line and a source line, respectively, and dummy cells disposed between the select gate transistors and the memory cells neighbored to them, wherein the dummy cells are set in a threshold voltage distribution higher than the erased threshold voltage of the memory cell by combination of a first program state and a second program state, the first program state being for boosting the threshold voltage of the dummy cells with a program voltage applied while the second program state being for suppressing an increase of the threshold voltage of the dummy cells in comparison with the first program state after reaching a certain threshold level, wherein the dummy cell is programmed in the first program state with the program voltage applied thereto under the condition that a first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the first program state, and wherein the dummy cell is programmed in the second program state with the program voltage applied thereto under the condition that a second bit line control voltage higher than the first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the second program state. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor memory device comprising:
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a memory cell array with NAND cell units arranged therein, the NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit to a bit line and a source line, respectively, and dummy cells disposed between the select gate transistors and the memory cells neighbored to them, wherein the memory cells and the dummy cells in the NAND cell unit are erased in a lump, and then subject to soft-program to be set at an erase state with a certain threshold voltage distribution, in which an over erase state has been dissolved, wherein the dummy cells in the NAND cell unit are, after erasing the memory cells and before or after soft-programming thereof, programmed to have a higher threshold voltage distribution than the memory cells, wherein the dummy cells are programmed by combination of a first program state and a second program state, the first program state being for boosting the threshold voltage of the dummy cells with a program voltage applied thereto while the second program state being for suppressing an increase of the threshold voltage of the dummy cells in comparison with the first program state after reaching a certain threshold level, wherein the dummy cell in the first program state is programmed with the program voltage applied thereto under the condition that a first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the first program state, and wherein and the dummy cell in the second program state is programmed with the program voltage applied under thereto the condition that a second bit line control voltage higher than the first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the second program state. - View Dependent Claims (8, 9, 10)
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11. A method for erasing a semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit to a bit line and a source line, respectively, and dummy cells disposed between the select gate transistors and the memory cells neighbored to them, comprising:
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erasing the memory cells and the dummy cells in an erase unit; soft-programming the memory cells and the dummy cells in the erase unit for dissolving over-program state thereof; and programming the dummy cells in the erase unit with a first program state and a second program state for setting the dummy cells in a threshold voltage higher than the erased threshold voltage of the memory cells, the first program state being for boosting the threshold voltage of the dummy cells with a program voltage applied while the second program state being for suppressing an increase of the threshold voltage of the dummy cells in comparison with the first program state after reaching a certain threshold level, wherein the dummy cell is programmed in the first program state with the program voltage applied thereto under the condition that a first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the first program state, and wherein the dummy cell is programmed in the second program state with the program voltage applied thereto under the condition that a second bit line control voltage higher than the first bit line control voltage is transferred from the bit line to the channel of the NAND cell unit through the select gate transistor, the select gate transistor being kept on during the second program state. - View Dependent Claims (12, 13, 14, 15)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsHosono, Koji
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Primary Examiner(s)Lam; David
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Application NumberUS11/987,716Publication NumberTime in Patent Office735 DaysField of Search365/185.2, 365/185.09, 365/185.17, 365/185.18, 365/185.24, 365/185.29, 365/185.33US Class Current365/185.2CPC Class CodesG11C 16/3418 Disturbance prevention or e...
