Nand-structured flash memory

• US 7,630,261 B2
• Filed: 06/28/2007
• Issued: 12/08/2009
• Est. Priority Date: 02/17/2004
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hara, Takahiko, Fukuda, Koichi, Maejima, Hiroshi, Abe, Takumi
• Primary Examiner(s): Nguyen; Dang T
• Application Number:
  US11/770,252
• Publication Number:
  US 20070279981A1
• Time in Patent Office: 894 Days
• Field of Search: 365/210, 365/185.17, 365/185.23, 365/185.18, 365/185.29, 365/185.14, 365/185.2, 365/230.06
• US Class Current: 365/210.1
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor, a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate, a dummy gate driving circuit controlling a potential of the control gate of the dummy gate, and a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing the external data.

Claims

1. A NAND-structured flash memory comprising:

a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line;

at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor;

a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate;

a dummy gate driving circuit controlling a potential of the control gate of the at least one dummy gate; and

a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing the external data,

wherein

nonvolatile memories forming the nonvolatile memory linked unit are quaternary memories,

the at least one dummy gate includes a first dummy gate adjacent to the bit line or the source line, and a second dummy gate disposed between the first dummy gate and the nonvolatile memory linked unit, and

a potential lower than that supplied to a second control gate of the second dummy gate is supplied to a first control gate of the first dummy gate.

2. The NAND-structured flash memory according to claim 1, wherein a non-selected potential is always supplied to the control gate of the at least one dummy gate.

3. A NAND-structured flash memory comprising:

a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line;

at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor;

a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate;

a dummy gate driving circuit controlling a potential of the control gate of the at least one dummy gate; and

a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing the external data,

wherein

nonvolatile memories forming the nonvolatile memory linked unit are quaternary memories,

the at least one dummy gate includes two dummy gates, and

the two dummy gates operate as binary nonvolatile memories.

4. The NAND-structured flash memory according to claim 3, wherein the dummy gate has parity data which is written therein.

5. The NAND-structured flash memory according to claim 3, wherein information on whether the nonvolatile memory linked unit is in an erased state or written state is written in the dummy gate.