Frequency synchronisation of clocks

• US 7,630,407 B2
• Filed: 02/20/2003
• Issued: 12/08/2009
• Est. Priority Date: 02/22/2002
• Status: Active Grant

• Current Assignee: Sony Europe BV (Sony Group Corp.)
• Original Assignee: Sony United Kingdom Limited (Sony Group Corp.)
• Inventors: Olday, Stephen Charles, Compton, Matthew
• Primary Examiner(s): Phunkulh; Bob A
• Application Number:
  US10/371,902
• Publication Number:
  US 20030174734A1
• Time in Patent Office: 2,483 Days
• Field of Search: 370/509, 370/503, 370/516, 375/356
• US Class Current: 370/509
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04N 21/242 Synchronization processes, e.g. processing of PCR [Program Clock References] arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083

Abstract

The frequency of a local clock of a local data processor in communication with an asynchronous switched packet network is synchronized to the frequency of a reference clock of a source data processor also coupled to the network. Timing packets each including a field containing the destination address of the local processor and a field containing reference clock data indicating the time at which the packet is launched onto the network are sent to the local data processor from the source data processor across the network. The frequency of the local clock is controlled in dependence on the reference clock data and the times of arrival of the packets.

Claims

1. A method of synchronising a frequency of a local clock of a local data processor in communication with an asynchronous switched packet network to a frequency of a reference clock of a source data processor also coupled to the network, the method comprising the steps of:

sending, to the local data processor from the source data processor across the network, data packets including a field containing a destination address of the local processor and a field containing reference clock data indicating a time at which a data packet is launched onto the network; and

controlling the frequency of the local clock in dependence on the reference clock data and times of arrival of the data packets by controlling the local clock in dependence on an error signal which is dependent on a) a difference between the reference clock data in successively received data packets containing the reference clock data and b) a difference between local clock data indicating the local clock time at times of receipt of said data packets.

2. A method according to claim 1, wherein said data packets contain video data.

3. A method according to claim 1, further comprising:

sensing, with the source data processor, when the network has capacity to send timing data; and

sending the timing data when said capacity exists.

4. A method according to claim 1, further comprising:

counting, with a reference counter included in the source processor, ticks of the reference clock and said reference clock data is a count in the reference counter at a time at which a data packet containing the reference clock data is sent across the network.

5. A method according to claim 4, further comprising:

controlling the local clock in dependence on an error signal which is dependent on a) a difference between the reference clock data in successively received data packets containing the reference clock data and b) a difference between local clock data indicating the local clock time at times of receipt of said data packets containing the reference clock data; and

counting, with a local counter included in the local processor, which counts ticks of the local clock and said local clock data is a count in the local counter of the local processor at a time of receipt of a data packet containing reference clock data.

6. A method according to claim 5, further comprising:

low pass filtering said error signal.

7. A method according to claim 6, further comprising:

accumulating the filtered error signal and controlling the local clock in dependence on the accumulated filtered error signal.

8. A method according to claim 1, wherein the network comprises a plurality of local processors having respective addresses, the method comprising sending said data packets containing the reference clock data to two or more of the local processors.

9. A method according to claim 8, further comprising:

sending, to a group of the local processors having a group address, data packets containing the reference clock data each including a field containing the group address, and a field containing the said reference clock data.

10. A method according to claim 8, further comprising:

sending, to local processors of the network having a broadcast address, data packets containing the reference clock data that each include a field containing the broadcast address and a field containing said reference clock data.

11. A method according to claim 1, wherein if there is a failed data packet which is not successfully transmitted at the source data processor or not successfully received at the local data processor, then the error signal is dependent on a) a difference between the reference clock data of a first data packet received prior to the unsuccessful transmission or reception of the failed data packet and the reference clock data in a second data packet received after the unsuccessful transmission or reception of the failed data packet and b) a difference between local clock data indicating the local clock time at times of receipt of said first data packet and said second data packet.

12. A data processor comprising:

a reference clock;

a source of data processed synchronously with the reference clock;

a generator of data packets including said synchronously processed data, reference clock data and an address field containing address data indicating the destination of a data packet; and

an interface for sending the data packets across an asynchronous switched network to a receiving data processor, the reference clock data indicating a time at which a data packet is launched onto the network,

wherein the receiving data processor has a local clock and a control system for controlling a frequency of the local clock in dependence on the reference clock data and times of arrival of the data packets at the data processor by controlling the local clock in dependence on an error signal which is dependent on a) a difference between the reference clock data in successively received data packets containing the reference clock data and b) a difference between local clock data indicating the local clock time at times of receipt of said data packets.

13. A data processor according to claim 12, further comprising:

a reference counter which counts ticks of the reference clock and said reference clock data is a count in the counter at a time a data packet containing the reference clock data is launched onto the network.

14. A data processor according to claim 12, further comprising:

a sensing unit configured to sense when the network has capacity to send timing data and to cause the data processor to send the timing data when said capacity exists.

15. A network card comprising a data processor according to claim 12.

16. A data processor comprising:

a local clock; and

an interface configured to receive, from an asynchronous switched network, data packets which contain data produced synchronously with a reference clock and timing data indicating a reference clock time at a time a data packet was launched onto the network and an address field containing address data indicating an address of the data processor, and configured to pass the timing data to a control system for controlling a frequency of the local clock in dependence on the reference clock data and times of arrival of the data packets at the data processor by controlling the local clock in dependence on an error signal which is dependent on a) a difference between the reference clock data in successively received data packets containing the reference clock data and b) a difference between local clock data indicating the local clock time at times of receipt of said data packets.

17. A data processor according to claim 16, wherein the control system comprises a counter which counts ticks of the local clock and said local clock data is a count in the counter at a time of receipt of a data packet containing reference clock data.

18. A data processor according to claim 16, further comprising:

a low pass filter configured to filter said error signal.

19. A data processor according to claim 18, further comprising:

an accumulator configured to accumulate the filtered error signal and controlling the local clock in dependence on the accumulated filtered error signal.

20. A data processor according to claim 16, further comprising:

a data processing device configured to process data synchronously with the local clock and wherein said interface is configured to receive data from the network and pass it to the data processing device.

21. A data processor according to claim 20, further configured to receive data packets containing both timing data and said data and to pass the timing data to the control system and the data to the data processor.

22. A data processor according to claim 20, wherein said data processing device is a video processing device.

23. A network card comprising a data processor according to claim 16.

24. An asynchronous switched network comprising:

a plurality of nodes to at least one of which is coupled a source data processor comprising a reference clock, a source of data processed synchronously with the reference clock, a generator of data packets comprising said synchronously processed data, reference clock data and an address field containing address data indicating a destination of a packet, and an interface for sending the data packets across an asynchronous switched network, the reference clock data indicating a time at which a data packet is launched onto the network, and the at least one of the plurality of nodes is connected to a local data processor comprising a local clock, an interface for receiving, from an asynchronous switched network, data packets which contain timing data each indicating a reference clock time at the time a data packet was launched onto the network and an address field containing address data indicating an address of the source data processor, and for passing the timing data to a control system for controlling a frequency of the local clock in dependence on the reference clock data and times of arrival of the data packets at the local data processor and linking the said source and local data processors by controlling the local clock in dependence on an error signal which is dependent on a) a difference between the reference clock data in successively received data packets containing the reference clock data and b) a difference between local clock data indicating the local clock time at times of receipt of said data packets.

25. An asynchronous switched network according to claim 24, further comprising:

a plurality of local data processors connected to respective nodes of the network, each of said local data processors comprising a local clock, an interface for receiving, from an asynchronous switched network, packets containing the reference clock data which contain timing data each indicating a reference clock time at the time a data packet was launched onto the network and an address field containing address data indicating the address of a source data processor, and for passing timing data to a control system for controlling a frequency of the local clock in dependence on the reference clock data and times of arrival of the data packets containing the reference clock data at a local data processor, the source data processor being operable to send data packets containing the reference clock data to two or more local processors.

26. An asynchronous switched network according to claim 25, wherein a group of local processors has a group address and the source data processor is operable to send data packets containing the reference clock data to the group of local processors, the data packets containing the reference clock data having a field containing group addresses and a field containing the said reference clock data.

27. An asynchronous switched network according to claim 25, wherein the source data processor configured to send data packets containing the reference clock data to local data processors connected to the network, the data packets containing the reference clock data each include a field containing a broadcast address and a field containing reference clock data.