Device for transmitting data between memories

• US 7,631,153 B2
• Filed: 07/28/2006
• Issued: 12/08/2009
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Mahrla, Peter, Goedecke, Michael, Barstow, John
• Primary Examiner(s): Peugh; Brian R
• Assistant Examiner(s): BRADLEY, MATTHEW A
• Application Number:
  US11/460,888
• Publication Number:
  US 20070028030A1
• Time in Patent Office: 1,229 Days
• Field of Search: 711/154
• US Class Current: 711/154
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

An apparatus for data transmission between memories has a memory controller as well as a memory protocol controller. In one embodiment, a first memory controller is operatively connected to a first memory, and a memory protocol controller is operatively connected between the first memory controller and a second memory, wherein the first memory is a volatile memory and the second memory is a nonvolatile memory. The volatile memory includes a command list containing a command sequence for the memory protocol controller. The memory protocol controller may be configured to produce at least one of an error detection code and an error correction code when an error condition occurs.

Claims

1. An apparatus for data transmission between a first memory and a second memory, the apparatus comprising:

a first memory controller operatively connected to the first memory; and

a memory protocol controller operatively connected between the first memory controller and the second memory, wherein the first memory is a volatile memory and the second memory is a nonvolatile memory, wherein a command list containing a command sequence for controlling the memory protocol controller is stored in the first memory, and wherein the command list in the first memory includes commands for the memory protocol controller and additionally commands for the nonvolatile memory,

wherein the first memory controller is a direct memory access controller configured such that;

commands from the command list are transmitted by the direct memory access controller to the non-volatile memory;

only memory protocol controller commands are interpreted by the memory protocol controller; and

each command for the non-volatile memory is preceded by a command to output to the non-volatile memory, whereby commands for the non-volatile memory are passed to the non-volatile memory.

2. The apparatus of claim 1, wherein the first memory controller is a direct memory access controller.

3. The apparatus of claim 1, further comprising a second memory controller connected in series with the memory protocol controller and the first memory controller.

4. The apparatus of claim 3, wherein the memory protocol controller is disposed between the first and second memory controllers, and wherein the first memory controller is a direct memory access controller and the second memory controller is a conventional memory controller.

5. The apparatus of claim 1, wherein data to be transmitted from the volatile memory to the non-volatile memory is at least one of:

stored in a separate list in the volatile memory; and

stored as part of the command list in the volatile memory.

6. The apparatus of claim 1, wherein, once the memory protocol controller has carried out a command, the memory protocol controller passes a request for a next command on a command request line of the direct memory access controller, wherein the direct memory access controller then transmits the next command from the volatile memory to the memory protocol controller, and wherein this sequence is repeated until the direct memory access controller comes to an end of the command list.

7. The apparatus of claim 6, further comprising:

a microprocessor configured such that the direct memory access controller passes an interrupt signal to the microprocessor at the end of the command list as a signal for indicating that the task has been carried out completely.

8. The apparatus of claim 7, wherein the start of data transmission is initiated by the microprocessor by setting a run bit in the memory protocol controller when the command list in the volatile memory has been set up completely, and wherein, thereafter, the data transmission process takes place without any further microprocessor control unless error conditions occur.

9. The apparatus of claim 8, wherein the memory protocol controller provides a signal indicating an occurrence of error condition to the microprocessor, wherein a cause of an error and an address of a respective last command to be carried out are read by the microprocessor from a status register, and wherein all further requests after the error condition are output to the direct memory access controller.

10. The apparatus of claim 9, wherein the memory protocol controller is configured to produce at least one of an error detection code and an error correction code for the error condition.

11. The apparatus of claim 10, wherein, for read operations, the memory protocol controller compares the error detection code produced during the read operation with a stored error detection code stored in the non-volatile memory, and wherein, for a read error, the memory protocol controller performs one of correcting the error condition and triggering an interrupt to the microprocessor.

12. The apparatus of claim 10, wherein, for write operations, the memory protocol controller produces the error correction code and writes the error correction code to a predetermined point in the non-volatile memory.

13. The apparatus of claim 1, further comprising:

at least one control line connecting the memory protocol controller directly to the non-volatile memory.

14. The apparatus of claim 1, wherein the data is transmitted in data packets.

15. The apparatus of claim 1, wherein the memory protocol controller includes a data buffer.

16. The apparatus of claim 1, wherein the memory protocol controller is configured to carry out data compression and data decompression for at least one of write operations and read operations.

17. The apparatus of claim 1, further comprising:

a microprocessor, wherein the memory protocol controller is configured to signal error conditions to the microprocessor.