Method and apparatus for supporting vector operations on a multi-threaded microprocessor

• US 7,631,171 B2
• Filed: 12/19/2005
• Issued: 12/08/2009
• Est. Priority Date: 12/19/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Kroeger, Robert J., Bonebakker, Jan L.
• Primary Examiner(s): Chan; Eddie P
• Assistant Examiner(s): Partridge; William B
• Application Number:
  US11/312,853
• Publication Number:
  US 20070143574A1
• Time in Patent Office: 1,450 Days
• Field of Search: 712 2- 9, 712/227, 712/209, 703/26, 717/136, 717/138
• US Class Current: 712/227
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

One embodiment of the present invention provides a system that supports vector operations on a multi-threaded microprocessor. During operation, the system detects a vector instruction in a program. The system maps this vector instruction onto the thread contexts of the multi-threaded microprocessor. As part of the mapping process, the system splits the vector instruction across a set of threads that execute in parallel and generates a set of instructions for the set of threads. This mapping process allows the vector instruction to be executed efficiently across multiple threads.

Claims

1. A method for supporting vector operations on a non-vector multi-threaded microprocessor, comprising:

while executing a program, detecting a vector instruction in the program; and

mapping the vector instruction onto the non-vector multi-threaded microprocessor, wherein the non-vector multi-threaded microprocessor does not include vector registers or enough processor registers to enable performing an operation on a vector of arguments in a single instruction;

wherein mapping the vector instruction comprises using at least one of a just-in-time compiler, a trap-handling system, an instruction emulation system, or a library to distribute one or more sub-operations from the vector instruction across a set of threads, within one or more processor cores, that execute in parallel in different thread contexts on the non-vector multi-threaded microprocessor and generating a set of instructions for the set of threads from the sub-operations.

2. The method of claim 1, wherein mapping the vector instruction comprises adjusting the number of threads across which the vector instruction is mapped to provide a variable vector size.

3. The method of claim 2, wherein variable vector size allows multiple vector instructions to execute simultaneously on different sets of threads which execute concurrently on different processor cores within a non-vector multi-threaded, multi-core microprocessor.

4. The method of claim 3,

wherein multiple non-vector multi-threaded microprocessors are coupled together by a shared memory structure;

and

wherein sets of threads from the multiple non-vector multi-threaded microprocessors can be combined virtually to create a larger variable vector size for vector instructions.

5. The method of claim 1,

wherein all of the threads in the set of threads execute the same shared set of instructions but operate on different data;

and

wherein each thread tracks where it is currently executing in the shared set of instructions.

6. The method of claim 1, wherein supporting vector operations on the non-vector multi-threaded microprocessor allows legacy vector program code to be executed on the non-vector multi-threaded microprocessor.

7. The method of claim 1, wherein supporting vector operations on the non-vector multi-threaded microprocessor allows programs to be written in terms of vector operations.

8. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for supporting vector operations on a non-vector multi-threaded microprocessor the method comprising:

while executing a program, detecting a vector instruction in the program; and

mapping the vector instruction onto the non-vector multi-threaded microprocessor, wherein the non-vector multi-threaded microprocessor does not include vector registers or enough processor registers to enable performing an operation on a vector of arguments in a single instruction;

wherein mapping the vector instruction comprises using at least one of a just-in-tune compiler, a trap-handling system, an instruction emulation system, or a library to distribute one or more sub-operations from the vector instruction across a set of threads, within one or more processor cores, that execute in parallel in different thread contexts on the non-vector multi-threaded microprocessor and generating a set of instructions for the set of threads from the sub-operations.

9. The computer-readable storage medium of claim 8, wherein mapping the vector instruction comprises adjusting the number of threads across which the vector instruction is mapped to provide a variable vector size.

10. The computer-readable storage medium of claim 9, wherein variable vector size allows multiple vector instructions to execute simultaneously on different sets of threads which execute concurrently on different processor cores within a non-vector multi-threaded, multi-core microprocessor.

11. The computer-readable storage medium of claim 10,

wherein multiple non-vector multi-threaded microprocessors are coupled together by a shared memory structure;

and

wherein sets of threads from the multiple non-vector multi-threaded microprocessors can be combined virtually to create a larger variable vector size for vector instructions.

12. The computer-readable storage medium of claim 8,

wherein all of the threads in the set of threads execute the same shared set of instructions but operate on different data;

and

wherein each thread tracks where it is currently executing in the shared set of microprocessor instructions.

13. The computer-readable storage medium of claim 8, wherein supporting vector operations on the non-vector multi-threaded microprocessor allows legacy vector program code to be executed on the non-vector multi-threaded microprocessor.

14. The computer-readable storage medium of claim 8, wherein supporting vector operations on the non-vector multi-threaded microprocessor allows such programs to be written in terms of vector operations.

15. An apparatus for supporting vector operations on a non-vector multi-threaded microprocessor comprising:

a detection mechanism configured to detect a vector instruction in a program while executing the program; and

a mapping mechanism configured to map the vector instruction onto the multi-threaded microprocessor, wherein the non-vector multi-threaded microprocessor does not include vector registers or enough processor registers to enable performing an operation on a vector of arguments in a single instruction;

wherein mapping the vector instruction comprises using at least one of a just-in-time compiler, a trap-handling system, an instruction emulation system, or a library to distribute one or more sub-operations from the vector instruction across a set of threads, within one or more processor cores, that execute in parallel in different thread contexts on the non-vector multi-threaded microprocessor and generating a set of instructions for the set of threads from the sub-operations.

16. The apparatus of claim 15, wherein mapping the vector instruction comprises adjusting the number of threads across which the vector instruction is mapped to provide a variable vector size.

17. The apparatus of claim 16, wherein variable vector size allows multiple vector instructions to execute simultaneously on different sets of threads which execute concurrently on different processor cores within a non-vector multi-threaded, multi-core microprocessor.

18. The apparatus of claim 17,

wherein multiple non-vector multi-threaded microprocessors are coupled together by a shared memory structure;

and

wherein sets of threads from the multiple non-vector multi-threaded microprocessors can be combined virtually to create a larger variable vector size for vector instructions.