Semiconductor device and manufacturing method thereof

• US 7,633,085 B2
• Filed: 04/07/2005
• Issued: 12/15/2009
• Est. Priority Date: 03/29/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kusuyama, Yoshihiro, Suzawa, Hideomi
• Primary Examiner(s): Nguyen; Thinh T
• Application Number:
  US11/101,315
• Publication Number:
  US 20050200767A1
• Time in Patent Office: 1,713 Days
• Field of Search: 257/40, 257/59, 257/72, 257/330, 257/764, 257/642, 257/759, 257/E21.024, 257/E31.004, 257/E39.007, 438/640, 438/82, 438/99, 438/48, 438/128, 438/149, 438/151, 438/157, 438/283
• US Class Current: 257/40
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.

Claims

1. A semiconductor device comprising:

an insulating substrate;

at least one thin film transistor formed over the insulating substrate, the thin film transistor including at least a channel region, source and drain regions with the channel region therebetween, a gate insulating film adjacent to the channel region, and a gate electrode adjacent to the channel region with the gate insulating film interposed therebetween;

a first conductive film formed over the thin film transistor and connected with one of the source region and drain region;

a first inorganic insulating film covering said first conductive film;

a second inorganic insulating film covering the first inorganic insulating film;

an organic resin film covering the second inorganic insulating film;

a contact hole that goes through the first inorganic insulating film, the second inorganic insulating film and the organic resin film;

an inner side surface of the contact hole of the first and the second inorganic insulating films being a taper like having an angle range of 30 degree to 80 degree from a horizontal surface, the inner side surface being in contact with a bottom surface of the contact hole; and

a second conductive film formed over the organic resin film and connected to said first conductive film at the bottom surface of the contact hole;

wherein the second conductive film is a pixel electrode, and

wherein a lower side end portion of the organic resin film in the contact hole is aligned with an upper side portion of the second inorganic insulating film in the contact hole.

2. The semiconductor device according to claim 1, wherein the semiconductor device includes an active matrix liquid crystal display device, an active matrix EL display device or an active matrix EC display device.

3. The semiconductor device according to claim 1, wherein the organic resin film is an organic-based SiO compound film.

4. The semiconductor device according to claim 1, wherein each of the first and second inorganic insulating films is a silicon nitride film or a silicon oxide nitride film.

5. The semiconductor device according to claim 1, wherein the second inorganic insulating film is thinner than the first inorganic insulating film.

6. The semiconductor device according to claim 1, wherein the organic resin film is formed of polyimide, acrylic, polyamide, polyimide-amide, or BCB (benzocyclobutene).

7. The semiconductor device according to claim 1, wherein the thin film transistor is top-gate type.

8. A semiconductor device comprising:

an insulating substrate;

at least one thin film transistor formed over the insulating substrate, the thin film transistor including at least a channel region, source and drain regions with the channel region therebetween, a gate insulating film adjacent to the channel region, and a gate electrode adjacent to the channel region with the gate insulating film interposed therebetween;

a first conductive film formed over the thin film transistor and connected with one of the source region and drain region;

a first inorganic insulating film covering the first conductive film;

a second inorganic insulating film covering the first inorganic insulating film;

an organic resin film covering the second inorganic insulating film;

a contact hole that goes through the first inorganic insulating film, the second inorganic insulating film and the organic resin film;

an inner side surface of the contact hole of the first and the second inorganic insulating films and the organic resin film having taper angles from a horizontal surface; and

a second conductive film formed over the organic resin film and connected to the first conductive film at a bottom surface of the contact hole,

wherein the taper angle of the inner side surface of the contact hole of the first and second inorganic insulating films has an angle range of 30 degree to 80 degree, the inner side surface being in contact with the bottom surface of the contact hole,

wherein the second conductive film is a pixel electrode, and

wherein a lower side edge portion of the inner surface of the organic resin film is intersected with an upper side edge portion of the inner surface of the second inorganic insulating film.

9. The semiconductor device according to claim 8, wherein the semiconductor device includes an active matrix liquid crystal display device, an active matrix EL display device or an active matrix EC display device.

10. The semiconductor device according to claim 8, wherein the organic resin film is an organic-based SiO compound film.

11. The semiconductor device according to claim 8, wherein each of the first and second inorganic insulating films is a silicon nitride film or a silicon oxide nitride film.

12. The semiconductor device according to claim 8, wherein the second inorganic insulating film is thinner than the first inorganic insulating film.

13. The semiconductor device according to claim 8, wherein the organic resin film is formed of polyimide, acrylic, polyamide, polyimide-amide, or BCB (benzocyclobutene).

14. The semiconductor device according to claim 8, wherein the thin film transistor is a top-gate type.

15. A semiconductor device comprising:

an insulating substrate;

at least one thin film transistor formed over the insulating substrate, the thin film transistor including at least a channel region, source and drain regions with the channel region therebetween, a gate insulating film adjacent to the channel region, and a gate electrode adjacent to the channel region with the gate insulating film interposed therebetween;

a first conductive film formed over the thin film transistor and connected with one of the source region and drain region;

a first inorganic insulating film covering the first conductive film;

a second inorganic insulating film covering the first inorganic insulating film;

an organic resin film covering the second inorganic insulating film;

a contact hole that goes through the first inorganic insulating film, the second inorganic insulating film and the organic resin film;

an inner side surface of the contact hole of the first and the second inorganic insulating films and the organic resin film having taper angles from a horizontal surface; and

a second conductive film formed over the organic resin film and connected to the first conductive film at a bottom surface of the contact hole,

wherein the taper angle of the inner side surface of the contact hole of the first and second inorganic insulating films has an angle range of 30 degree to 80 degree, the inner side surface being in contact with the bottom surface of the contact hole,

wherein the second inorganic insulating film is 20 to 50 nm in thickness,

wherein the second conductive film is a pixel electrode, and

wherein a lower side edge portion of the inner surface of the organic resin film is intersected with an upper side edge portion of the inner surface of the second inorganic insulating film.

16. The semiconductor device according to claim 15, wherein the semiconductor device includes an active matrix liquid crystal display device, an active matrix EL display device or an active matrix EC display device.

17. The semiconductor device according to claim 15, wherein the organic resin film is an organic-based SiO compound film.

18. The semiconductor device according to claim 15, wherein each of the first and second inorganic insulating films is a silicon nitride film or a silicon oxide nitride film.

19. The semiconductor device according to claim 15, wherein the second inorganic insulating film is thinner than the first inorganic insulating film.

20. The semiconductor device according to claim 15, wherein the organic resin film is formed of polyimide, acrylic, polyamide, polyimide-amide, or BCB (benzocyclobutene).

21. The semiconductor device according to claim 15, wherein the thin film transistor is a top-gate type.