Trench MOSFET with implanted drift region

• US 7,633,121 B2
• Filed: 10/31/2007
• Issued: 12/15/2009
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Original Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Inventors: Hshieh, Fwu-Iuan
• Primary Examiner(s): Dang; Phuc T
• Application Number:
  US11/981,072
• Publication Number:
  US 20090108338A1
• Time in Patent Office: 776 Days
• Field of Search: 257/288, 257/330, 257/401, 438/242, 438/268, 438/274
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees.

Claims

1. A trenched semiconductor power device comprising a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions, said trenched semiconductor power device further comprising:

tilt-angle implanted drift regions surrounding said trenched gate below said body regions for on-resistance reduction, and preventing a degraded breakdown voltage with a thick oxide in lower portion of trench sidewall and bottom; and

said semiconductor power device further comprising a N-channel MOSFET device having N-type tilt-angle implanted drift regions in an N-epitaxial layer supported on a N+ substrate.

2. The trenched semiconductor power device of claim 1 further comprising:

guard rings disposed at a termination area for operating at a breakdown voltage greater than fifty volts in a range substantially between fifty to two hundred volts.

3. The trenched semiconductor power device of claim 1 wherein:

a field plate disposed at a termination area for operating at a breakdown voltage ranging between eight volts to fifty volts.

4. The trenched semiconductor power device of claim 1 wherein:

each of said trenched gates having a thicker oxide layer on sidewalls of a lower portion of said trenched gates and a thinner oxide layer on sidewalls at an upper portion of said trenched gates.

5. The trenched semiconductor power device of claim 1 wherein:

said N-epitaxial layer having a resistivity ranging between 0.3 to 3.0 mohm-cm and said trenched semiconductor power device having a breakdown voltage ranging between 8 to 200V volts.

6. A trenched semiconductor power device comprising a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions, said trenched semiconductor power device further comprising:

tilt-angle implanted drift regions surrounding said trenched gate below said body regions for on-resistance reduction, and preventing a degraded breakdown voltage with a thick oxide in lower portion of trench sidewall and bottom; and

said semiconductor power device further comprising a P-channel MOSFET device having P tilt-angle implanted drift regions in a P-epitaxial layer supported on a P+ type substrate.

7. The trenched semiconductor power device of claim 6 further comprising:

guard rings disposed at a termination area for operating at a breakdown voltage greater than fifty volts in a range substantially between fifty to two hundred volts.

8. The trenched semiconductor power device of claim 6 further comprising:

a field plate disposed at a termination area for operating at a breakdown voltage ranging between eight volts to fifty volts.

9. The trenched semiconductor power device of claim 6 wherein:

each of said trenched gates having a thicker oxide layer on sidewalls of a lower portion of said trenched gates and a thinner oxide layer on sidewalls at an upper portion of said trenched gates.

10. The trenched semiconductor power device of claim 6 wherein:

said P-epitaxial layer having a resistivity ranging between 0.3 to 3.0 mohm-cm and said trenched semiconductor power device having a breakdown voltage ranging between 8 to 200V volts.

11. A trenched semiconductor power device comprising a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions, said trenched semiconductor power device further comprising:

tilt-angle implanted drift regions surrounding said trenched gate below said body regions for on-resistance reduction, and preventing a degraded breakdown voltage with a thick oxide in lower portion of trench sidewall and bottom; and

each of said trenched gates further includes a bottom portion having a smaller width and padded with a thicker gate oxide layer on sidewalls of said trenched gates and a top portion having a greater width and padded with a thinner gate oxide layer on sidewalls of said trenched gates.

12. The trenched semiconductor power device of claim 11 wherein:

each of said bottom gate segments is padded by a thicker oxide layer on sidewalls of a lower portion of said trenched gates and each of said top gate segments is padded by a thinner oxide layer on sidewalls at an upper portion of said trenched gates.

13. A trenched semiconductor power device comprising a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions, said trenched semiconductor power device further comprising:

tilt-angle implanted drift regions surrounding said trenched gate below said body regions for on-resistance reduction, and preventing a degraded breakdown voltage with a thick oxide in lower portion of trench sidewall and bottom; and

each of said trenched gates further includes a bottom gate segment and a top gate segment insulated by an inter-segment insulation layer wherein the bottom gate segment is connected to a source metal and the upper gate segment is connected to a gate pad.