Semiconductor device and manufacturing method of the same

• US 7,633,133 B2
• Filed: 12/15/2006
• Issued: 12/15/2009
• Est. Priority Date: 12/15/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okada, Kazuo, Yamada, Hiroshi, Noma, Takashi, Morita, Yuichi, Kitagawa, Katsuhiko, Okubo, Noboru, Shinogi, Hiroyuki, Ishibe, Shinzo, Okigawa, Mitsuru, Otsuka, Shigeki
• Primary Examiner(s): Jackson, Jr.; Jerome
• Assistant Examiner(s): Chen; Yu
• Application Number:
  US11/639,411
• Publication Number:
  US 20070145590A1
• Time in Patent Office: 1,096 Days
• Field of Search: 257431-435, 257/436, 257/448, 257/459, 257/692, 257/773, 257/778, 257/466, 257/E31.122, 257/E31.124, 257/E23.114
• US Class Current: 257/434
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/10 Bump connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

This invention provides a semiconductor device that solves a problem that a pattern of a wiring formed on a back surface of a semiconductor substrate is reflected on an output image. A light receiving element (e.g. a CCD, an infrared ray sensor, a CMOS sensor, or an illumination sensor) is formed on a front surface of a semiconductor substrate, and a plurality of ball-shaped conductive terminals is disposed on a back surface of the semiconductor substrate. Each of the conductive terminals is electrically connected to a pad electrode on the front surface of the semiconductor substrate through a wiring layer. The wiring layer and the conductive terminal are formed on the back surface of the semiconductor substrate except in a region overlapping the light receiving element in a vertical direction, and are not disposed in a region overlapping the light receiving element.

Claims

1. A semiconductor device comprising:

a semiconductor substrate comprising a front surface and a back surface;

a light receiving element formed on the front surface of the semiconductor substrate;

a transparent substrate attached to the front surface of the semiconductor substrate so as to cover the light receiving element;

a plurality of wiring layers formed on the back surface of the semiconductor substrate so that no one wiring layer is in a path of light passing through the transparent substrate and the light receiving element;

a protection layer covering the wiring layers; and

a reflection layer made of a metal and formed on the back surface of the semiconductor substrate so as to be in the path of the light passing through the transparent substrate and the light receiving element.

2. The semiconductor device of claim 1, wherein the protection layer comprises an infrared ray absorbent material.

3. The semiconductor device of claim 1, wherein the reflection layer and the wiring layers comprise the same metal.

4. The semiconductor device of claim 1, further comprising a pad electrode connected with the light receiving element, wherein one of the wiring layers extends from the back surface along a side surface of the semiconductor substrate so as to be in contact with the pad electrode.

5. The semiconductor device of claim 1, further comprising a pad electrode formed on the front surface of the semiconductor substrate, wherein the semiconductor substrate has a via hole penetrating the semiconductor substrate from the back surface to reach the pad electrode and one of the wiring layers is connected with the pad electrode through the via hole.

6. The semiconductor device of claim 5, further comprising a conductive terminal disposed on one of the wiring layers through an opening formed in the protection layer so that the conductive terminal does not overlap the via hole in plan view of the semiconductor device.

7. The semiconductor device of claim 1, further comprising a dummy electrode not connected to the light receiving element and formed on the back surface of the semiconductor substrate.

8. A semiconductor device comprising:

a semiconductor substrate comprising a first region and a second region, the first region comprising a first front surface and a first back surface, and the second region comprising a second front surface and a second back surface;

a light receiving element formed on the first front surface;

a plurality of wiring layers formed on the second back surface and connected with the light receiving element;

a transparent substrate attached to the first and second front surfaces; and

a protection layer covering the wiring layers,

wherein no wiring connected with the light receiving element is formed on the first back surface, and all wiring layers connected with the light receiving element are disposed on one side of the light receiving element in plan view of the semiconductor device.

9. The semiconductor device of claim 8, further comprising a reflection layer formed on the first back surface.

10. The semiconductor device of claim 8, further comprising a dummy electrode not connected to the light receiving element and formed on the first back surface of the semiconductor substrate on another side of the light receiving element opposite from said one side in the plan view of the semiconductor device.