Semiconductor package

• US 7,633,144 B1
• Filed: 05/24/2006
• Issued: 12/15/2009
• Est. Priority Date: 05/24/2006
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Youn Sang, Kim, Bong Chan, Kim, Yoon Joo
• Primary Examiner(s): Sefer; A.
• Assistant Examiner(s): Parker; Allen L
• Application Number:
  US11/440,662
• Time in Patent Office: 1,301 Days
• Field of Search: 257/E21.504, 257/687, 257/723, 257/678
• US Class Current: 257/678
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Disclosed are a semiconductor package and a method of making the same. In the semiconductor package, a substrate and a semiconductor die are covered with and encapsulated by vertically pressing thermosetting resin having fluidity in a predetermined temperature range and denaturalizing itself in gel. Thus, it is possible to reduce a thickness of the semiconductor package and prevent wire sweeping.

Claims

1. A semiconductor package comprising:

a substrate, which has a plurality of conductive patterns formed on upper and lower surfaces of the substrate and a solder mask layer formed on the lower surface of the substrate;

a semiconductor die adhered by adhesive to the upper surface of the substrate;

a plurality of conductive wires for electrically connecting die pads on an upper surface of the semiconductor die to bond fingers on the upper surface of the substrate;

encapsulant pressed downward over an upper portion of the semiconductor die so as to cover the semiconductor die placed on the upper surface of the substrate and the conductive wires, wherein the encapsulant covers only a first part of the semiconductor die and only a first part of the conductive wires leaving a second part of the semiconductor die and a second part of the conductive wires exposed to an exterior of the semiconductor package through a space portion existing at a side of the semiconductor package, wherein the first part of the conductive wires comprises the entire upper portion of the conductive wires above a plane defined by the upper surface of the semiconductor die; and

a plurality of solder balls fusion-welded to the conductive pattern formed on the lower surface of the substrate.

2. The semiconductor package as claimed in claim 1, wherein the encapsulant includes an adhering portion made of thermosetting resin having fluidity in a predetermined temperature range.

3. The semiconductor package as claimed in claim 1, further comprising a second semiconductor die adhered to the upper surface of the semiconductor die, wherein the encapsulant covers at least a part of the second semiconductor die.

4. The semiconductor package as claimed in claim 3, wherein the encapsulant covers the entire second semiconductor die and the upper surface of the semiconductor die.

5. The semiconductor package as claimed in claim 3, wherein the second semiconductor die is smaller than the semiconductor die.

6. The semiconductor package as claimed in claim 2, wherein the encapsulant includes a supporting portion that is located on an upper surface of the adhering portion so as to support the adhering portion.

7. The semiconductor package as claimed in claim 1, wherein at least one semiconductor die is stacked.

8. The semiconductor package as claimed in claim 1, wherein the conductive wires have one end bonded to the die pads in a stitch bonding manner and the other end attached to the bond fingers in a ball bonding manner.

9. A semiconductor package comprising:

a substrate;

a semiconductor die coupled to an upper surface of the substrate;

conductive wires electrically connecting die pads on an upper surface of the semiconductor die to bond fingers on the upper surface of the substrate;

an encapsulant covering the semiconductor die and the conductive wires, wherein the encapsulant covers only a first part of the semiconductor die and only a first part of the conductive wires leaving a second part of the semiconductor die and a second part of the conductive wires exposed to an exterior of the semiconductor package through a space portion existing at a side of the semiconductor package, wherein the first part of the semiconductor die comprises the upper surface of the semiconductor die and an upper portion of sides of the semiconductor die, wherein the second part of the semiconductor die comprises a lower portion of the sides of the semiconductor die, the encapsulant comprising;

an adhering portion made of thermosetting resin having fluidity in a predetermined temperature range; and

a supporting portion that is located on an upper surface of the adhering portion, the supporting portion supporting the adhering portion, the supporting portion having a lower surface with a total area identical with the total area of the upper surface of the adhering portion, the supporting portion being selected from the group consisting of polyimide and epoxy.

10. The semiconductor package as claimed in claim 9, further comprising a second semiconductor die adhered to the upper surface of the semiconductor die, wherein the encapsulant covers the second semiconductor die.

11. The semiconductor package as claimed in claim 10, wherein the encapsulant covers the entire second semiconductor die and the upper surface of the semiconductor die.

12. The semiconductor package as claimed in claim 10, wherein the second semiconductor die is smaller than the semiconductor die.

13. The semiconductor package as claimed in claim 12, wherein the second semiconductor die is adhered to the upper surface of the semiconductor die inward of the die pads.

14. The semiconductor package as claimed in claim 9, wherein the conductive wires have one end bonded to the die pads in a stitch bonding manner and the other end attached to the bond fingers in a ball bonding manner.

15. A semiconductor package comprising:

a substrate;

a semiconductor die coupled to an upper surface of the substrate;

a second semiconductor die coupled to an upper surface of the semiconductor die;

conductive wires electrically connecting die pads of the semiconductor die and the second semiconductor die to bond fingers on the upper surface of the substrate;

an encapsulant covering at least a part of the second semiconductor die, wherein the encapsulant covers only a first part of the second semiconductor die leaving a second part of the second semiconductor die and the semiconductor die exposed to an exterior of the semiconductor package through a space portion existing at a side of the semiconductor package, wherein the first part of the second semiconductor die comprises an upper surface of the second semiconductor die and an upper portion of sides of the second semiconductor die, wherein the second part of the second semiconductor die comprises a lower portion of the sides of the second semiconductor die, the encapsulant comprising;

an adhering portion made of thermosetting resin having fluidity in a predetermined temperature range; and

a supporting portion that is located on an upper surface of the adhering portion, the supporting portion supporting the adhering portion, the supporting portion having a lower surface with a total area identical with the total area of the upper surface of the adhering portion, the supporting portion being selected from the group consisting of polyimide and epoxy.