Multistage tuning-tolerant equalizer filter with improved detection mechanisms for lower and higher frequency gain loops

• US 7,633,354 B2
• Filed: 08/31/2006
• Issued: 12/15/2009
• Est. Priority Date: 09/09/2005
• Status: Expired due to Fees

• Current Assignee: Vrije Universiteit Brussel
• Original Assignee: Vrije Universiteit Brussel
• Inventors: Kuijk, Maarten, Maillard, Xavier, Van den Brande, Koen
• Primary Examiner(s): Jones; Stephen E
• Application Number:
  US11/991,640
• Publication Number:
  US 20090128239A1
• Time in Patent Office: 1,202 Days
• Field of Search: 333/28.R, 333/18, 327/553, 375/229, 375/230, 375/232, 375/233
• US Class Current: 333/28.00R
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

The present invention provides an equalizer filter for compensating a received distorted signal for frequency dependent signal modifications introduced by a transmission channel, the received signal having an amplitude. The filter comprises at least one amplifying compensation stage having a gain and a saturation level, at least one limiting amplifier, and gain control means for controlling the gain of the at least one amplifying compensation stage, the gain control means comprising at least one comparator circuit comparing filtered input and output signals of the limiting amplifier, the at least one comparator circuit comprising a bias current source. The bias current source is adapted to deliver a variable current.

Claims

1. An equalizer filter for compensating a received distorted signal for frequency dependent signal modifications introduced by a transmission channel, the received signal having an amplitude, said filter comprising

at least one amplifying compensation stage having a gain and a saturation level,

at least one limiting amplifier,

gain control means for controlling the gain of the at least one amplifying compensation stage, the gain control means comprising a plurality of comparator circuits comparing filtered input and output signals of the limiting amplifier, the plurality of comparator circuits comprising a bias current source,

wherein the bias current source is adapted to deliver a variable current and the bias current is increased during periods when voltage levels of signals to be compared are the highest.

2. An equalizer filter according to claim 1, wherein the adaptation to the bias current source includes providing a current source delivering a current so low that the high frequency common mode rejection is deteriorated.

3. An equalizer filter according to claim 1, the gain control means comprising at least two comparator circuits comparing filtered input and output signals of the limiting amplifier, the at least two comparator circuits comprising a common bias current source.

4. An equalizer filter according to claim 1, wherein the adaptation to the current source is so as to provide a higher current level when differences between filtered input and output signals of the limiting amplifier are maximal.

5. An equalizer filter according to claim 1, wherein the gain of the at least one amplifying compensation stage is monotonically rising over at least a last decade in frequency below an upper data frequency of the received signal, the upper data frequency being at least half the data bandwidth or communication bit rate.

6. An equalizer filter according to claim 1, wherein the gain control means is adapted for controlling the gain of the amplifying compensation stage, such that the amplitude of the received signal amplified in the at least one amplifying compensation stage remains below the saturation level of the amplifying compensation stage.

7. An equalizer filter according to claim 1, wherein the equalizer filter is a dual loop equalizer filter.

8. An equalizer filter according to claim 1, wherein the equalizer filter is a triple loop equalizer filter.

9. An equalizer system for compensating a received distorted signal for frequency dependent signal modifications introduced by a transmission channel, said equalizer system comprising an equalizer filter according to claim 1.

10. An equalizer filter according to claim 1, wherein the plurality of comparator circuits comprise two differential inputs.

11. An equalizer filter according to claim 10, each differential input comprising two input nodes, wherein the comparator circuit is adapted to compare, from each differential input, signals on those input nodes which are highest in voltage.

12. An equalizer filter according to claim 11, wherein each input node of a differential input is connected to a gate of a transistor element.

13. An equalizer filter according to claim 1, wherein the adaptation to the current source includes the current source being provided with modulation means for modulating a current delivered by the bias current source.

14. An equalizer filter according to claim 13, wherein the modulation means for modulating the current delivered by the bias current source comprises a capacitive element placed in parallel over a fixed bias current source.

15. An equalizer filter according to claim 13, wherein the modulation means for modulating the current delivered by the bias current source comprises a modulation signal for modulating a variable current source.

16. A method for compensating a distorted signal for frequency dependent signal modifications introduced by a transmission channel, the signal having an amplitude, the method comprising

receiving a distorted signal,

compensating said distorted signal

outputting a compensated signal at an output node of an equalizer filter, wherein the step of compensating comprises

providing a gain,

amplifying the received signal in at least one amplifying compensation stage using the provided gain,

comparing differential outputs of a first signal on an output node of the last amplifying compensation stage and of a second signal on the output node of the equalizer filter, the comparing being adapted so that comparison performance is increased during periods when voltage levels of signals to be compared are the highest by increasing bias current of a comparator circuit.

17. A method according to claim 16, comprising before comparing the differential outputs, filtering the first signal on the output node of the last amplifying compensation stage and the second signal on the output node of the equalizer filter.

18. A method according to claim 16, furthermore comprising amplifying and/or saturating the output of the last amplifying compensation stage.

19. A method according to claim 16, furthermore comprising generating a comparison signal and using this comparison signal in adjusting at least one of the higher frequency gain, the mid-frequency gain or the low frequency gain of the at least one amplifying compensation stages.

20. A method according to any of claim 16, wherein the provided gain is monotonically rising over at least a last decade in frequency below an upper data frequency of the received distorted signal, the upper data frequency being at least half the data bandwidth or communication bit rate.

21. A method according to claim 16, wherein the gain is adapted so as to keep the amplitude of the signal below a saturation level of at least one amplifying compensation stage.