Parallel pipeline graphics system

• US 7,633,506 B1
• Filed: 11/26/2003
• Issued: 12/15/2009
• Est. Priority Date: 11/27/2002
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Demers, Eric, Leather, Mark M.
• Primary Examiner(s): Harrison; Chante
• Assistant Examiner(s): SAMS (LAY), MICHELLE L
• Application Number:
  US10/724,384
• Time in Patent Office: 2,211 Days
• Field of Search: 345/506, 345/505, 345/519
• US Class Current: 345/506
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on screen. Unlike prior single pipeline implementation, some embodiments use two or four parallel pipelines, though other configurations having 2^n pipelines may be used. When geometry data is sent to the back-end, it is divided up and provided to one of the parallel pipelines. Each pipeline is a component of a raster back-end, where the display screen is divided into tiles and a defined portion of the screen is sent through a pipeline that owns that portion of the screen'"'"'s tiles. In one embodiment, each pipeline comprises a scan converter, a hierarchical-Z unit, a z buffer logic, a rasterizer, a shader, and a color buffer logic.

Claims

1. A graphics chip comprising:

a front-end in the graphics chip configured to receive one or more graphics instructions and to output a geometry;

a back-end in the graphics chip configured to receive said geometry and to process said geometry into one or more final pixels to be placed in a frame buffer;

wherein said back-end in the graphics chip comprises multiple parallel pipelines;

wherein said geometry is determined to locate in a portion of an output screen defined by a tile; and

wherein each of said parallel pipelines further comprises a unified shader that is programmable to perform both color shading and texture shading.

2. The graphics chip of claim 1 wherein each of said parallel pipelines further comprises:

a FIFO unit for load balancing said each of said pipelines.

3. The graphics chip of claim 1 wherein each of said parallel pipelines further comprises:

a z buffer logic unit; and

a color buffer logic unit.

4. The graphics chip of claim 3 wherein said z buffer logic unit interfaces with said scan converter through a hierarchical Z interface and an early Z interface.

5. The graphics chip of claim 3 wherein said z buffer logic unit interfaces with said unified shader through a late Z interface.

6. The graphic chip of claim 1 comprising a setup unit for directing said geometry into one of said multiple parallel pipelines wherein said geometry is determined to locate in a portion of an output screen defined by a tile.

7. The graphics chip of claim 1 wherein each pipeline further comprises:

a scan converter;

a rasterizer; and

a texture unit.

8. The graphics chip of claim 1 wherein the unified shader is operative to operative to apply a programmed sequence of instructions to rasterized values and is operative to loop back to process operations for color shading and/or texture address shading.

9. The graphics chip of claim 1 wherein the unified shader is operative to apply a programmed sequence of instructions such that a first set of instructions are executed to perform color shading and a second set of instructions are executed to perform texture shading.

10. A method for processing computer graphics comprising:

receiving one or more graphics instructions in a front-end of a graphics chip and outputting a geometry;

receiving said geometry in a back-end of the graphics chip;

processing said geometry into one or more final pixels to be placed in a frame buffer,

wherein said back-end comprises multiple parallel pipelines;

using a setup unit to direct said geometry into one of said multiple parallel pipelines;

wherein said geometry is determined to locate in a portion of an output screen defined by a tile; and

wherein each of said parallel pipelines further comprises a unified shader and where the unified shader performs both color shading and texture shading based on programmable instructions.

11. The method of claim 10 further comprising:

using a FIFO unit for load balancing each of said pipelines.

12. The method of claim 10 wherein each of said parallel pipelines further comprises:

a z buffer logic unit; and

a color buffer logic unit.

13. The method of claim 12 wherein said z buffer logic unit interfaces with said scan converter through a hierarchical Z interface and an early Z interface.

14. The method of claim 12 wherein said z buffer logic unit interfaces with said unified shader through a late Z interface.

15. The method of claim 10 wherein the unified shader applies a programmed sequence of instructions to rasterized values and loops back to process operations for color shading and/or texture address shading.

16. The method of claim 10 wherein the unified shader applies a programmed sequence of instructions such that a first set of instructions are executed to perform color shading and a second set of instructions are executed to perform texture shading.

17. A computer program product comprising:

a computer usable medium having computer readable program code embodied therein configured to process computer graphics, said computer program product comprising;

computer readable code configured to cause a computer to receive one or more graphics instructions in a front-end of a graphics chip and output a geometry;

computer readable code configured to cause a computer to receive said geometry in a back-end of a graphics chip;

computer readable code configured to cause a computer to process said geometry into one or more final pixels to be placed in a frame buffer,

wherein said back-end comprises multiple parallel pipelines;

computer readable code configured to use a setup unit to direct said geometry into one of said multiple parallel pipelines;

wherein said geometry is determined to locate in a portion of an output screen defined by a tile; and

wherein each of said parallel pipelines further comprises a unified shader that is programmable to perform both color shading and texture shading.

18. The computer program product of claim 17 wherein said computer readable code configured to cause a computer to process further comprises:

computer readable code configured to cause a computer to use a FIFO unit for load balancing each of said pipelines.

19. The computer program product of claim 17 wherein each of said parallel pipelines further comprises:

a z buffer logic unit; and

a color buffer logic unit.

20. The computer program product of claim 19 wherein said z buffer logic unit interfaces with said scan converter through a hierarchical Z interface and an early Z interface.

21. The computer program product of claim 19 wherein said z buffer logic unit interfaces with said unified shader through a late Z interface.