M+N bit programming and M+L bit read for M bit memory cells
First Claim
1. A method of operating a memory, comprising:
- programming a selected memory cell of the memory to correspond to a selected state of a number of logic window states utilizing a selected programming threshold voltage level of a number of programming threshold voltage levels;
wherein the number of logic window states is determined by dividing a usable threshold voltage range of the memory cell into a number of threshold voltage ranges; and
wherein the number of programming threshold voltage levels is determined by dividing the usable threshold voltage range of the memory cell into the number of programming threshold voltage ranges, each having a corresponding nominal threshold voltage level, where the number of programming threshold voltage ranges is greater than the number of logic window states of the memory cell.
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Accused Products
Abstract
A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
79 Citations
25 Claims
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1. A method of operating a memory, comprising:
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programming a selected memory cell of the memory to correspond to a selected state of a number of logic window states utilizing a selected programming threshold voltage level of a number of programming threshold voltage levels; wherein the number of logic window states is determined by dividing a usable threshold voltage range of the memory cell into a number of threshold voltage ranges; and wherein the number of programming threshold voltage levels is determined by dividing the usable threshold voltage range of the memory cell into the number of programming threshold voltage ranges, each having a corresponding nominal threshold voltage level, where the number of programming threshold voltage ranges is greater than the number of logic window states of the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of operating a memory, comprising:
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accessing one or more selected memory cells and determining a nominal sensing threshold voltage level state associated with a programmed threshold voltage of each memory cell; wherein a number of nominal sensing threshold voltage levels is determined by dividing a usable threshold voltage range of each of the one or more selected memory cells into a number of sensing ranges, each of the sensing ranges having a corresponding nominal sensed threshold voltage level; and wherein the number of sensing threshold voltage ranges is greater than a number of logic window states of each of the one or more selected memory cells. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A non-volatile memory, comprising:
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a non-volatile memory array having a plurality of non-volatile memory cells; and a control circuit; wherein the non-volatile memory is adapted to program M+N bits of program data in each memory cell of a first number of non-volatile memory cells in a programming operation, where M is a number of user data bits stored in a defined number of threshold voltage logic window ranges of the memory cell and N is a number of additional programming ranges; and wherein the non-volatile memory is adapted to sense M+L bits of read data from each memory cell of a second number of non-volatile memory cells in a read operation, where M is the number of user data bits being read from the defined number of threshold voltage logic window ranges of the memory cell and L is a number of additional nominal sensing voltage ranges being sensed in the read operation. - View Dependent Claims (16, 17, 18)
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19. A method of operating a memory, comprising:
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grouping two or more memory cells into an associated unit of memory cells; and programming data into a number of defined threshold voltage logic window states of each of the two or more memory cells of the associated unit of memory cells; wherein a usable threshold voltage range of one or more memory cells of the associated unit of memory cells is divided into a non-binary number of defined threshold voltage logic window states; and wherein the programmed data is stored across the associated unit of memory cells by being encoded into a total number of available threshold voltage logic window states in the associated unit of memory cells. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A non-volatile memory, comprising:
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a non-volatile memory array having a plurality of non-volatile memory cells; and a control circuit; wherein the non-volatile memory is adapted to; associate a plurality of associated groups of memory cells, each associated group of memory cells having two or more non-volatile memory cells, wherein a threshold voltage range of each associated group of memory cells is divided into a non-binary number of defined threshold voltage logic window states, and program data into the non-binary number of defined threshold voltage logic window states of the two or more memory cells of a selected associated group of memory cells, wherein the programmed data is stored across the associated group of memory cells by being encoded into a total number of available threshold voltage logic window cell states in the associated group of memory cells.
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Specification