Redundancy scheme in memory

• US 7,633,800 B2
• Filed: 08/08/2007
• Issued: 12/15/2009
• Est. Priority Date: 08/08/2007
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Adusumilli, Vijay P., Telecco, Nicola
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US11/835,572
• Publication Number:
  US 20090040825A1
• Time in Patent Office: 860 Days
• Field of Search: 365/185.09, 365/185.12, 365/189.12, 365/200
• US Class Current: 365/185.09
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time.

Claims

1. A method comprising:

transferring normal data bytes and redundant column data bytes from a Flash memory chip into a page register in the Flash memory chip, wherein the redundant column data bytes contain one or more correct bits for corresponding defective FLASH memory cells;

transferring to a shift register in a companion control chip the redundant column data bytes from the page register in the Flash memory chip, the companion control chip being separated from the Flash memory chip;

fetching into the companion control chip the normal data bytes from the page register of the FLASH memory chip;

checking in the companion control chip if an address for a fetched normal data byte is for a defective memory location;

if none of the bits of a fetched normal data byte is from a defective memory cell, storing that normal data byte in a page register in the companion control chip;

if at least one of bits of the fetched normal data byte is from a defective memory cell, combining in the companion control chip the normal data byte with a corresponding redundant data byte to provide a correct data byte with correct bits for an external user.

2. The method of claim 1 wherein checking in the companion control chip includes using a look-up table with the addresses of defective FLASH memory cells to determine redundant addresses for data bytes.

3. The method of claim 2 wherein the look-up table identifies the addresses of one or more bits, nibbles, or bytes to be replaced by appropriate bits stored in the redundant shift register in the companion control chip.

4. The method of claim 1 wherein data is fetched a byte at a time into the companion control chip the normal data bytes from the page register of the FLASH memory chip.

5. The method of claim 1 including determining the address of bad data storage locations and pre-loading those addresses into fuses in the memory chip.

6. The method of claim 3 including pre-fetching the addresses of defective Flash memory cells that are pre-loaded into fuses in the memory chip and loading those addresses of bad data storage locations into the companion controller chip.

7. The method of claim 4 including shifting the redundant bits out of the page registers during a micro control read mode of operation.

8. The method of claim 1 including packaging the separate control chip in the same integrated-circuit package as the memory chip.

9. A method comprising:

storing in a companion control chip addresses for defective FLASH memory cells of a FLASH memory chip, the companion control chip being separated from the FLASH memory chip;

comparing addresses of incoming data bits to the addresses for defective FLASH memory cells, wherein said comparing includes using a look-up table with the addresses of defective FLASH memory cells to determine redundant addresses for data bytes, and wherein the look-up table identifies the addresses of one or more bits, nibbles, or bytes to be replaced by appropriate bits stored in the redundant shift register in the companion control chip;

if an incoming data bit for a defective FLASH memory cell is received, storing a corresponding data bit in a redundant byte register in the companion control chip;

transferring data bytes for non-defective memory cells into a page register in the FLASH memory chip; and

subsequently transferring the contents of the redundant byte register into redundant columns in the page register in the FLASH memory chip.

10. The method of claim 9 wherein data is fetched a byte at a time into the companion control chip the normal data bytes from the page register of the FLASH memory chip.

11. The method of claim 9 including determining the address of bad data storage locations and pre-loading those addresses into fuses in the memory chip.

12. The method of claim 9 including pre-fetching the addresses of defective Flash memory cells that are pre-loaded into fuses in the memory chip and loading those addresses of bad data storage locations into the companion controller chip.

13. The method of claim 9 including shifting the redundant bits out of the page registers during a micro control read mode of operation.

14. The method of claim 9 including packaging the separate control chip in the same integrated-circuit package as the memory chip.

15. A method comprising:

storing in a companion control chip addresses for defective FLASH memory cells of a FLASH memory chip, the companion control chip being separated from the FLASH memory chip;

for a read mode of operation;

transferring to a shift register in the companion control chip the redundant column data bytes from the page register in the Flash memory chip;

checking in the companion control chip if an address for a fetched normal data byte is for a defective memory location;

if at least one of bits of the fetched normal data byte is from a defective memory cell, combining in the companion control chip the normal data byte with a corresponding redundant data byte to provide a corrected data byte with correct bits;

reading out to an external user the data bytes from non-defective memory cells and corrected data bytes;

for a program mode of operation;

comparing addresses of incoming data bits to the addresses for defective FLASH memory cells;

if an incoming data bit for a defective FLASH memory cell is received, storing a corresponding data bit in a redundant byte register in the companion control chip;

transferring data bytes for non-defective memory cells into a page register in the FLASH memory chip; and

subsequently transferring the contents of the redundant byte register into redundant columns in the page register in the FLASH memory chip.

16. The method of claim 15 including transferring normal data bytes and redundant column data bytes from the Flash memory chip into a page register in the Flash memory chip, wherein the redundant column data bytes contain one or more correct bits for corresponding defective FLASH memory cells.

17. The method of claim 15 including fetching into the companion control chip the normal data bytes from the page register of the FLASH memory chip.

18. The method of claim 15 including if none of the bits of a fetched normal data byte is from a defective memory cell, storing that normal data byte in a page register in the companion control chip.

19. The method of claim 15 including:

testing the memory device to find the defective memory cell in the memory device;

storing in fuses in the memory device the memory cell address for the defective memory cell;

transferring the address information of the faulty memory cell from the fuses in the memory device into the control device.