Semiconductor memory device, operational processing device and storage system
First Claim
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1. A semiconductor device comprising:
- a first memory,a second memory arranged separately from said first memory, and storing information different in attribute from storage information of said first memory,a third memory including first and second memory regions each having a plurality of memory cells each nonvolatilely storing information by using characteristics other than a threshold voltage, and arranged corresponding to the first and second memories, each memory region for caching the storage information of a corresponding memory, said first and second memory regions having storage capacities being variable within a storage capacity of said third memory,a transfer control circuit for controlling data transfer between said first and second memories and said first and second memory regions, andan operational processing circuit executing using the storage information.
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Abstract
A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.
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Citations
2 Claims
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1. A semiconductor device comprising:
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a first memory, a second memory arranged separately from said first memory, and storing information different in attribute from storage information of said first memory, a third memory including first and second memory regions each having a plurality of memory cells each nonvolatilely storing information by using characteristics other than a threshold voltage, and arranged corresponding to the first and second memories, each memory region for caching the storage information of a corresponding memory, said first and second memory regions having storage capacities being variable within a storage capacity of said third memory, a transfer control circuit for controlling data transfer between said first and second memories and said first and second memory regions, and an operational processing circuit executing using the storage information. - View Dependent Claims (2)
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Specification
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeRenesas Technology Corporation (Renesas Electronics Corporation)
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InventorsHidaka, Hideto
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Primary Examiner(s)TRAN, MICHAEL THANH
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Application NumberUS12/125,733Publication NumberTime in Patent Office572 DaysField of Search365/230.03, 365/230.06US Class Current365/230.03CPC Class CodesG11C 11/005 comprising combined but ind...
