Delay-locked loop with dynamically biased charge pump
First Claim
1. A delay-locked loop, comprising:
- a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output;
a charge pump system operatively coupled with the phase detector and including;
a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and
a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output;
a delay regulator coupled to the delay line and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of the delay line; and
a current compensation circuit coupled to the delay regulator and configured to operate in one of an activated state, in which the current compensation circuit draws current from the delay regulator, and a deactivated state, in which the current compensation circuit draws substantially no current from the delay regulator.
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Accused Products
Abstract
A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.
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Citations
22 Claims
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1. A delay-locked loop, comprising:
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a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output; a charge pump system operatively coupled with the phase detector and including; a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output; a delay regulator coupled to the delay line and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of the delay line; and a current compensation circuit coupled to the delay regulator and configured to operate in one of an activated state, in which the current compensation circuit draws current from the delay regulator, and a deactivated state, in which the current compensation circuit draws substantially no current from the delay regulator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A delay-locked loop, comprising:
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a first delay line; a second delay line; a phase detector coupled to outputs of the first and second delay lines, the phase detector including an UP output and a DOWN output; a charge pump coupled to the phase detector so that the UP output of the phase detector is coupled to a first charge pump input and so that the DOWN output of the phase detector is coupled to a second charge pump input, where the charge pump is configured to pump charge via a charge pump output based on a bias condition and on levels at the first charge pump input and the second charge pump input; a charge pump replica coupled with the charge pump and configured to dynamically adjust the bias condition so that, in response to an assertion condition at the first charge pump input and the second charge pump input, the charge pump pumps a net charge that tends toward a desired value associated with such assertion condition; a delay regulator coupled to at least one of the delay lines and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of said delay line; and a current compensation circuit coupled to the delay regulator and configured to operate in one of an activated state, in which the current compensation circuit draws current from the delay regulator, and a deactivated state, in which the current compensation circuit draws substantially no current from the delay regulator. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification