Delay-locked loop with dynamically biased charge pump

• US 7,634,039 B2
• Filed: 02/03/2006
• Issued: 12/15/2009
• Est. Priority Date: 02/04/2005
• Status: Active Grant

• Current Assignee: True Circuits, Inc.
• Original Assignee: True Circuits, Inc.
• Inventors: Kim, Jaeha, Hartman, Daniel Karl, Maneatis, John George
• Primary Examiner(s): Fan; Chieh M
• Assistant Examiner(s): Joseph; Jaison
• Application Number:
  US11/347,835
• Publication Number:
  US 20060193419A1
• Time in Patent Office: 1,411 Days
• Field of Search: 375/375, 375/376, 331/17, 327/149, 327/158
• US Class Current: 375/376
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses

Abstract

A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.

Claims

1. A delay-locked loop, comprising:

a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output;

a charge pump system operatively coupled with the phase detector and including;

a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and

a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output;

a delay regulator coupled to the delay line and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of the delay line; and

a current compensation circuit coupled to the delay regulator and configured to operate in one of an activated state, in which the current compensation circuit draws current from the delay regulator, and a deactivated state, in which the current compensation circuit draws substantially no current from the delay regulator.

2. The delay-locked loop of claim 1, where the phase detector is coupled to two delay lines, with the delay-locked loop being configured to lock the relative delay between the two delay lines to one reference cycle.

3. The delay-locked loop of claim 1, where the charge pump includes:

a first switch coupled with a first current source and configured to be actuated via assertion of an actuating signal from the UP output; and

a second switch coupled with a second current source and configured to be actuated via assertion of an actuating signal from the DOWN output, the charge pump being adapted so that biasing of the current sources and actuation of the switches controls pumping of charge from the charge pump system.

4. The delay-locked loop of claim 3, where the feedback control loop includes a charge pump replica, the charge pump replica having:

a first switch coupled with a first current source, the first switch and the first current source of the charge pump replica being matched to the first switch and the first current source of the charge pump; and

a second switch coupled with a second current source, the second switch and the second current source of the charge pump replica being matched to the second switch and the second current source of the charge pump.

5. The delay-locked loop of claim 4, where the first current source of the charge pump and the first current source of the charge pump replica are commonly biased, and where the second current source of the charge pump and the second current source of the charge pump replica are commonly biased.

6. The delay-locked loop of claim 5, where the first switch and the second switch of the charge pump replica are tied closed.

7. The delay-locked loop of claim 6, where an output of the charge pump is fed back through a differential amplifier to bias at least one of the first current sources and the second current sources, thereby dynamically generating a bias condition in which an output of the charge pump replica converges to an output of the charge pump.

8. The delay-locked loop of claim 1, further comprising a flip-stack NAND gate in each delay element of the delay line.

9. The delay-locked loop of claim 1, where the current compensation circuit is configured to operate in the activated state when substantially no current is being drawn from the delay regulator by the delay line.

10. The delay-locked loop of claim 9, where the current compensation circuit is configured so that, in the activated state, it draws current substantially equivalent to that drawn by the delay line when a signal edge is propagating through the delay line.

11. The delay-locked loop of claim 1, where the current compensation circuit is configured to operate in the deactivated state when a signal edge is propagating through the delay line.

12. The delay-locked loop of claim 1, further comprising first and second control loops, the first control loop being configured to control relative delay occurring between the two signals based on phase offset detection between rising edges of the two signals, the second control loop being configured to control relative delay occurring between the two signals based on phase offset detection between falling edges of the two signals.

13. A delay-locked loop, comprising:

a first delay line;

a second delay line;

a phase detector coupled to outputs of the first and second delay lines, the phase detector including an UP output and a DOWN output;

a charge pump coupled to the phase detector so that the UP output of the phase detector is coupled to a first charge pump input and so that the DOWN output of the phase detector is coupled to a second charge pump input, where the charge pump is configured to pump charge via a charge pump output based on a bias condition and on levels at the first charge pump input and the second charge pump input;

a charge pump replica coupled with the charge pump and configured to dynamically adjust the bias condition so that, in response to an assertion condition at the first charge pump input and the second charge pump input, the charge pump pumps a net charge that tends toward a desired value associated with such assertion condition;

a delay regulator coupled to at least one of the delay lines and adapted to supply a current-dependent regulated supply voltage to power semiconductor devices of said delay line; and

a current compensation circuit coupled to the delay regulator and configured to operate in one of an activated state, in which the current compensation circuit draws current from the delay regulator, and a deactivated state, in which the current compensation circuit draws substantially no current from the delay regulator.

14. The delay-locked loop of claim 13, where the assertion condition is a simultaneous assertion of activating signals at the first charge pump input and the second charge pump input.

15. The delay-locked loop of claim 14, where the desired value is substantially zero net charge.

16. The delay-locked loop of claim 13, where the charge pump and the charge pump replica each have a first common bias input and a second common bias input.

17. The delay-locked loop of claim 16, where the charge pump output and a charge pump replica output are coupled to a differential amplifier, and where an output of the differential amplifier biases at least one of the first common bias input and the second common bias input.

18. The delay-locked loop of claim 16, where the charge pump output and a charge pump replica output are operatively coupled to the first common bias input and the second common bias input.

19. The delay-locked loop of claim 13, where the current compensation circuit is configured to operate in the activated state when substantially no current is being drawn from the delay regulator by said delay line.

20. The delay-locked loop of claim 19, where the current compensation circuit is configured so that, in the activated state, it draws current substantially equivalent to that drawn by said delay line when a signal edge is propagating through said delay line.

21. The delay-locked loop of claim 13, where the current compensation circuit is configured to operate in the deactivated state when a signal edge is propagating through said delay line.

22. The delay-locked loop of claim 13, further comprising first and second control loops, the first control loop being configured to control relative delay occurring between the first and second delay lines based on phase offset detection between rising edges output from the first and second delay lines, the second control loop being configured to control relative delay occurring between the first and second delay lines based on phase offset detection between falling edges output from the first and second delay lines.