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Multi-threaded processing design in architecture with multiple co-processors

  • US 7,634,776 B2
  • Filed: 05/12/2005
  • Issued: 12/15/2009
  • Est. Priority Date: 05/13/2004
  • Status: Active Grant
First Claim
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1. A method for determining a mapping of a plurality of processing stages to a plurality of processors, which offers overall low average processing time to process input data, in a multimedia codec architecture, comprising the steps of:

  • identifying a chronological sequence of processing stages for processing said input data including identifying interdependencies of said processing stages;

    identifying a set of processing stages from said chronological sequence of processing stages for each of said processors based on suitability of each said processor to perform each of said processing stages;

    mapping each said processing stage to a respective processor based on said set of processing stages identified for each processor;

    staggering the processing stages for said mapping to accommodate said interdependencies resulting in a pipeline;

    ascertaining average processing time for said pipeline associated with said mapping;

    repeating the steps of mapping, staggering and ascertaining by changing mappings between the plurality of processing stages and the plurality of processors based on said set of processing stages identified for each processor to obtain a plurality of pipelines;

    choosing one design pipeline from said plurality of pipelines that offers overall low average processing time based on each of said mappings; and

    wherein said mapping of each said processing stage to a respective processor based on said set of processing stages identified for each processor comprises;

    assigning one or more data buffers to each processing stage on each processor, based on said interdependencies; and

    ,ensuring that the step of mapping is done based on a constraint that no two processors can access a given buffer simultaneously.

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