Etchant composition and manufacturing method for thin film transistor array panel

• US 7,635,436 B2
• Filed: 11/10/2005
• Issued: 12/22/2009
• Est. Priority Date: 02/15/2005
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Kwan-Tack, Kim, Kyu-Sang
• Primary Examiner(s): ALANKO, ANITA KAREN
• Application Number:
  US11/271,079
• Publication Number:
  US 20060183338A1
• Time in Patent Office: 1,503 Days
• Field of Search: None
• US Class Current: 216/23
• CPC Class Codes: C23F 1/20 for etching aluminium or alloys thereof
• CPC Class Codes: C23F 1/26 for etching refractory metals
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides an etchant composition containing 60 to 75 wt % of phosphoric acid (H₃PO₄), 0.5 to 15 wt % of nitric acid (HNO₃), 2 to 15 wt % of acetic acid (CH₃COOH), and 0.1 to 15 wt % of aluminum nitrate (Al(NO₃)₃).

Claims

1. A manufacturing method of a TFT array panel comprising:

forming a gate line made of a conductive material on an insulating substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer having a predetermined pattern on the gate insulating layer;

forming a data line and drain electrode made of a conductive material on the semiconductor layer; and

forming a pixel electrode connected to the drain electrode,

wherein at least one of the formation of the gate line, the formation of the data line and drain electrode, and the formation of the pixel electrode comprises an photo-etching with an etchant containing phosphoric acid (H₃PO₄), nitric acid (HNO₃), acetic acid (CH₃COOH), and aluminum nitrate (Al(NO₃)₃).

2. The method of claim 1, wherein the etchant comprises 60 to 75 wt % of phosphoric acid (H₃PO₄), 0.5 to 15 wt % of nitric acid (HNO₃), 2 to 15 wt % of acetic acid (CH₃COOH), and 0.1 to 15 wt % of aluminum nitrate (Al(NO₃)₃).

3. The method of claim 1, wherein the gate line and the data line and drain electrode comprise a first conductive layer made of an aluminum-containing conductive material and a second conductive layer made of a molybdenum-containing conductive material.

4. The method of claim 3, wherein the first conductive layer is made of Al—

Nd.

5. The method of claim 3, wherein the second conductive layer is made a Mo-alloy containing Mo and at least one metal selected from among niobium (Nb), tungsten (W), tantalum (Ta), and chromium (Cr).

6. The method of claim 3, wherein the second conductive layer is made of molybdenum nitride (MoN).

7. The method of claim 1, wherein the formation of the gate line comprises:

sequential deposition of a first conductive layer of Al containing material and a second conductive layer of molybdenum-containing material; and

photo-etching the second and first conductive layers.

8. The method of claim 1, wherein the formation of the data line and drain electrode comprises:

sequential deposition of a first conductive layer of molybdenum-containing material, a second conductive layer of Al containing material, and a third layer of molybdenum-containing material; and

photo-etching the third to first conductive layers.

9. The method of claim 8, wherein the first to third layers respectively have thicknesses of 200 to 1,000 Å

, 2,000 to 4,000 Å

, and 200 to 1,000 Å

.

10. The method of claim 1, wherein the formation of the pixel electrode comprises:

depositing an ITO or IZO layer; and

photo-etching the ITO or IZO layer.

11. The method of claim 1, wherein the data line and the semiconductor layer are formed by photo-etching using a photoresist pattern having a first portion, a second portion thicker than the first portion, and a third portion thinner than the first portion.

12. The method of claim 11, wherein the first portion is disposed between the source electrode and the drain electrode, and the second portion is disposed on the data line and the drain electrode.