Configurable tapered delay chain with multiple sizes of delay elements

• US 7,635,992 B1
• Filed: 12/23/2004
• Issued: 12/22/2009
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert Paul
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US11/021,222
• Time in Patent Office: 1,825 Days
• Field of Search: 326/112, 326/113, 326/119, 326/121, 326/122, 327/149, 327/161, 327/263, 327/276, 327/393, 327/395
• US Class Current: 326/112
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A tapered chain of delay elements. The chain of delay elements includes a plurality of delay elements comprising a plurality of smaller sized stacked inverter delay elements each configured to implement a first delay, and a plurality of larger sized stacked inverter delay elements each configured to implement a second delay larger than the first delay. A switch circuit is coupled to the plurality of delay elements and is configured to select at least one of the plurality of delay elements to create a delay signal path having an amount of delay in accordance with a number of delay elements comprising the delay signal path. An input is coupled to a first delay element of the delay signal path to receive an input signal. An output is coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Claims

1. A method of delaying a signal comprising:

selecting one of a plurality of delay elements using a switch circuit to create a delay signal path, wherein the plurality of delay elements comprise;

a first group of stacked inverter delay elements each configured to implement a first delay by incorporating a first number of active devices per delay element;

a second group of stacked inverter delay elements each configured to implement a second delay larger than the first delay by incorporating a second number of active devices per delay element, the second number larger than the first number; and

a third group of stacked inverter delay elements each configured to implement a third delay larger than the second delay by incorporating a third number of active devices per delay element, the third number larger than the second number;

coupling an input signal to a first delay element of the delay signal path using the switch circuit;

propagating the input signal through the delay signal path; and

receiving a resulting output signal from a last delay element of the delay signal path by using the switch circuit to generate a resulting output signal that is a

delayed version of the input signal.

2. The method of claim 1 wherein each of the plurality of delay elements is configured to add an incremental amount of delay to the input signal when switched into the delay signal path by the switch circuit.

3. The method of claim 1 wherein the switch circuit is configured to adjust an amount of delay for the delay signal path by adjusting a number of the plurality of delay elements in the delay signal path.

4. The method of claim 1 wherein the input signal propagates from a first delay element to a subsequent delay element using a substantially direct connection.

5. The method of claim 1 wherein the switch circuit is configured to store a plurality of configuration bits to select a number of delay elements comprising the delay signal path.

6. The method of claim 5 wherein an amount of delay added to the input signal is adjustable in accordance with setting the configuration bits in the switch circuit.

7. The method of claim 1 wherein each of the delay elements comprises a stacked inverter delay element.

8. A tapered chain of delay elements, comprising:

a plurality of delay elements comprising;

a first group of stacked inverter delay elements for implementing a first delay by incorporating a first number of active devices per delay element;

a second group of stacked inverter delay elements for implementing a second delay larger than the first delay by incorporating a second number of active devices per delay element, the second number larger than the first number; and

a third group of stacked inverter delay elements for implementing a third delay larger than the second delay by incorporating a third number of active devices per delay element, the third number larger than the second number;

a switch circuit coupled to the plurality of delay elements and configured to select at least one of the plurality of delay elements to create a delay signal path having an amount of delay in accordance with a number of delay elements comprising the delay signal path;

an input coupled to a first delay element of the delay signal path to receive an input signal; and

an output coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

9. The tapered chain of delay elements of claim 8, wherein each of the stacked inverter delay elements further comprises:

a first plurality of devices of a first type coupled in series;

a second plurality of devices of an opposite type coupled in series; and

wherein said first and said second pluralities of devices are coupled in series.

10. The tapered chain of delay elements of claim 9 wherein each of the plurality of stacked inverter delay elements are configured for a lower leakage current than an inverter comprising only two active devices.

11. The tapered chain of delay elements of claim 9 wherein a gate of each of the plurality of stacked inverter delay elements is coupled to receive the input signal.

12. The tapered chain of delay elements of claim 8 wherein the switch circuit is configured to adjust an amount of delay for the delay signal path by adjusting a number of the plurality of delay elements in the delay signal path.

13. The tapered chain of delay elements of claim 8 wherein each of the plurality of delay elements is configured to add an incremental amount of delay to the input signal when switched into the delay signal path by the switch circuit.

14. The tapered chain of delay elements of claim 8 wherein the input signal propagates from the first stacked inverter delay element to a subsequent stacked inverter delay element using a substantially direct connection.

15. The tapered chain of delay elements of claim 8 wherein the switch circuit is configured to store a plurality of configuration bits to select a number of delay elements comprising the delay signal path.

16. The tapered chain of delay elements of claim 15 wherein an amount of delay added to the input signal is adjustable in accordance with the setting of the configuration bits in the switch circuit.

17. A tapered chain of delay elements, comprising:

a plurality of delay elements comprising;

a first group of stacked inverter delay elements each configured to implement a first delay by incorporating a first number of active devices per delay element;

a second group of stacked inverter delay elements each configured to implement a second delay larger than the first delay by incorporating a second number of active devices per delay element, the second number larger than the first number; and

a third group of stacked inverter delay elements each configured to implement a third delay larger than the second delay by incorporating a third number of active devices per delay element, the third number larger than the second number;

a switch circuit coupled to each of the plurality of delay elements and configured to select at least one of the plurality of delay elements to create a delay signal path having an amount of delay in accordance with a number of delay elements comprising the delay signal path;

an input coupled to a first delay element of the delay signal path to receive an input signal; and

an output coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

18. The tapered chain of delay elements of claim 17 wherein the switch circuit is configured to adjust an amount of delay for the delay signal path by adjusting a number of the plurality of delay elements in the delay signal path.

19. The tapered chain of delay elements of claim 18 wherein each delay element comprising the delay signal path is configured to add the first delay, the second delay, or the third delay to the input signal in accordance with whether the each delay element is of the first group, the second group, or the third group of stacked inverter delay elements, respectively.

20. The tapered chain of delay elements of claim 19 wherein the input signal propagates from the first stacked inverter delay element to a subsequent stacked inverter delay element using a substantially direct connection.