TFT-LCD array substrate and method for manufacturing the same

• US 7,636,135 B2
• Filed: 09/11/2007
• Issued: 12/22/2009
• Est. Priority Date: 09/11/2006
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Wang, Zhangtao, Qiu, Haijun, Min, Tae Yup, Rim, Seung Moo
• Primary Examiner(s): Dickey; Thomas L
• Assistant Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US11/853,297
• Publication Number:
  US 20080061295A1
• Time in Patent Office: 833 Days
• Field of Search: 257/59, 257/72, 257/66, 257/E21.414, 257/E29.003, 438/59, 438149-160, 349/141, 349/143, 349/43, 349/46, 349/160, 349/129
• US Class Current: 349/43
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A TFT-LCD array substrate and a method for manufacturing the same are disclosed. In the TFT-LCD array substrate, a first insulating layer, a semiconductor layer, and an ohmic contact layer are formed sequentially on the gate line and the gate electrode, and the ohmic contact layer is formed on the source region and the drain region of the semiconductor layer and exposes the channel; a second insulating layer is formed on the substrate, covers the sidewalls of the gate line and gate electrode, the first insulating layer, the semiconductor layer, and the ohmic contact layer, and exposes the ohmic contact layer in the source region and the drain region; the data line, the source electrode, the pixel electrode, and the drain electrode are formed on the second insulating layer; a passivation layer is formed on the TFT, the gate line, and the data line and exposes the pixel electrode.

Claims

1. A thin film transistor liquid crystal display (TFT-LCD) array substrate, comprising:

a substrate;

a gate line and a data line formed on the substrate and intersecting with each other to define a pixel region;

a pixel electrode formed in the pixel region; and

a TFT that is formed on the substrate and has a gate electrode connected with the gate line, a source electrode connected with the data line, and a drain electrode connected with the pixel electrode,

wherein a first insulating layer, a semiconductor layer, and an ohmic contact layer are formed sequentially on the gate line and the gate electrode, and the ohmic contact layer is formed on a source region and a drain region of the semiconductor layer and exposes a channel;

wherein a second insulating layer is formed on the substrate, covers the sidewalls of the gate line and gate electrode, the first insulating layer, the semiconductor layer, and the ohmic contact layer, and exposes the ohmic contact layer in the source region and the drain region;

wherein the data line, the source electrode, the pixel electrode, and the drain electrode are formed on the second insulating layer, and the source electrode and the drain electrode contact the ohmic contact layer in the source region and the drain region through the exposure in the second insulating layer, respectively; and

wherein a passivation layer is formed on the TFT, the gate line and the data line, and exposes the pixel electrode.

2. The array substrate according to claim 1, further comprising a groove formed over the gate line, which cuts off the ohmic contact layer and the semiconductor layer over the gate line and exposes the first insulating layer.

3. The array substrate according to claim 2, wherein a pixel electrode material layer is formed on the first insulating layer exposed in the groove.

4. The array substrate according to claim 1, wherein the second insulating layer covers the channel, and forms the source electrode via hole and the drain electrode via hole which expose the ohmic contact layer in the source region and the drain region, respectively.

5. The array substrate according to claim 1, wherein the passivation layer covers the channel.

6. The array substrate according to claim 1, wherein the gate line, the gate electrode, the source electrode, the data line, and the drain electrode comprise a single-layer film of Cr, W, Ti, Ta, Mo, Al, or Cu, or a composite film of any combination of Cr, W, Ti, Ta, Mo, Al, and Cu.

7. The array substrate according to claim 1, wherein the first insulating layer, the second insulating layer, and the passivation layer comprise oxide, nitride or oxynitride.

8. A method for manufacturing a TFT-LCD array substrate, comprising steps of:

depositing sequentially on a substrate a gate metal layer, a first insulating layer, a semiconductor layer, and an ohmic contact layer and patterning the layers to form a gate line, a gate electrode, and a channel of a TFT on the substrate;

depositing a second insulting layer and patterning the second insulating layer to expose the ohmic contact layer in the source region and the drain region of the TFT;

depositing a source/drain metal layer, including over the second insulating layer, and patterning the source/drain metal layer to form a data line, a source electrode, and a drain electrode, wherein the data line and the gate line intersect with each other to define a pixel region, and the source electrode and the drain electrode contact the ohmic contact layer in the source region and the drain region through the exposure in the second insulating layer, respectively; and

depositing a passivation layer, and after patterning the passivation layer with a photoresist, depositing a pixel electrode material layer, and stripping off the photoresist as well as the pixel electrode material layer on the photoresist to form a pixel electrode.

9. The method according to claim 8, wherein the gate metal layer, the first insulating layer, the semiconductor layer, and the ohmic contact layer are patterned with a gray tone mask to form the gate line, the gate electrode and the channel of the TFT.

10. The method according to claim 9, wherein a gray tone photoresist pattern is formed on the substrate with the gray tone mask, the gray tone photoresist pattern comprises a photoresist fully retained region which corresponds to the gate line and gate electrode, a photoresist partially retained region which corresponds to the channel of the TFT, and a photoresist-free region.

11. The method according to claim 10, wherein the gate metal layer, the first insulating layer, the semiconductor layer and the ohmic contact layer are patterned with the gray tone photoresist pattern to form the gate line, and the gate electrode, the photoresist pattern is processed to remove the photoresist partially retained region and reduce the thickness of the photoresist fully retained region, and the ohmic contact layer is patterned to form the channel of the TFT.

12. The method according to claim 11, wherein after the removing the photoresist partially exposed region, over-etching is performed on the ohmic contact layer to form the channel of the TFT.

13. The method according to claim 8, wherein the second insulating layer covers the channel after patterning and forms the source electrode via hole and the drain electrode via hole to expose the ohmic contact layer in the source region and the drain region, respectively.

14. The method according to claim 8, wherein the second insulating layer exposes the source region and the drain region, and covers the channel, after patterning.

15. The method according to claim 8, wherein patterning the second insulating layer comprises forming a recess in the second insulating layer over the gate line to expose the ohmic contact layer, and patterning the passivation layer comprises removing the passivation layer over the recess and removing the ohmic contact layer and the semiconductor layer to expose the first insulating layer, so as to form a groove.

16. The method according to claim 15, wherein after stripping off the pixel electrode material layer on the passivation layer, the pixel electrode material layer is retained on the first insulating layer exposed in the groove.

17. The method according to claim 8, wherein patterning the second insulating layer comprises etching a portion of the second insulating layer over the gate line to form a recess and removing the ohmic contact layer and the semiconductor layer to expose the first insulating layer, so as to form a groove.

18. A TFT-LCD array substrate, comprising:

a substrate;

a gate line and a data line formed on the substrate and intersecting with each other to define a pixel region;

a pixel electrode formed in the pixel region; and

a TFT that is formed on the substrate and has a gate electrode connected with the gate line, a source electrode connected with the data line, and a drain electrode connected with the pixel electrode,

wherein a first insulating layer, a semiconductor layer, and an ohmic contact layer are formed sequentially on the gate line and the gate electrode, and the ohmic contact layer is formed on a source region and a drain region of the semiconductor layer and exposes a channel;

wherein a second insulating layer is formed on the substrate, covers the sidewalls of the gate line and gate electrode, the first insulating layer, the semiconductor layer, and the ohmic contact layer, and exposes the ohmic contact layer in the source region and the drain region;

wherein the data line, the source electrode, the pixel electrode, and the drain electrode are formed on the second insulating layer, and the source electrode and the drain electrode contact the ohmic contact layer in the source region and the drain region through the exposure in the second insulating layer, respectively;

wherein a passivation layer is formed on the TFT, the gate line, and the data line and exposes the pixel electrode; and

wherein a groove is formed over the gate line, which cuts off the ohmic contact layer and the semiconductor layer over the gate line and exposes the first insulating layer.

19. The array substrate according to claim 18, wherein the second insulating layer covers the channel and forms a source electrode via hole and a drain electrode via hole which expose the ohmic contact layer in the source region and the drain region, respectively.

20. The array substrate according to claim 18, wherein the passivation layer covers the channel.