Integrated circuit memory devices that support selective mode register set commands

• US 7,636,273 B2
• Filed: 10/29/2008
• Issued: 12/22/2009
• Est. Priority Date: 07/20/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoo, Chang-sik, Kyung, Kye-hyun, Lee, Kee-hoon
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US12/260,373
• Publication Number:
  US 20090059680A1
• Time in Patent Office: 419 Days
• Field of Search: 365/230.06, 365/230.08
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

Claims

1. An integrated circuit memory device comprising:

a memory cell array;

a mode register configured to store information defining an operational characteristic of the memory device;

a command decoder configured to accept a selective mode register set command responsive to an enable signal received on a predetermined pin of the integrated circuit memory device and to reject a selective mode register set command responsive to a disable signal received on the predetermined pin of the integrated circuit memory device during a selective mode register set operation, so that information of the selective mode register set command is saved to the mode register when the enable signal is received on the predetermined pin during the selective mode register set operation; and

a data input/output buffer configured to control writing of data to the memory cell array during a write operation and/or reading of data from the memory cell array during a read operation in accordance with the operational characteristic defined by the information saved in the mode register.

2. The integrated circuit memory device according to claim 1 wherein information of the selective mode register set command is not saved to the mode register when the disable signal is received on the predetermined pin during the mode register set operation.

3. An integrated circuit memory device according to claim 1 further comprising:

a data mask pin, wherein the data input/output buffer is configured to write data to the memory cell array responsive to an inactive mask signal received at the data mask pin during a write operation and to disable writing data to the memory cell array responsive to an active mask signal received at the data mask pin during a write operation, wherein the predetermined pin comprises the data mask pin.

4. An integrated circuit memory device according to claim 1 further comprising:

a plurality of data input/output pins wherein the data input/output buffer is configured to write data from the data input/output pins to the memory cell array during a write operation and to read data from the memory cell array to the data input/output pins during a read operation, wherein the predetermined pin comprises one of the data input/output pins.

5. An integrated circuit memory device according to claim 1 wherein the predetermined pin is non-functional during read and write operations.

6. An integrated circuit memory device according to claim 1 further comprising:

a data strobe pin, wherein the data input/output buffer is configured to write data to the memory cell array responsive to a data strobe signal received at the data strobe pin during a write operation, and wherein the predetermined pin comprises the data strobe pin.

7. An integrated circuit memory device according to claim 1 further comprising:

an internal clock signal generator configured to generate an internal clock signal responsive to a system clock signal received at a clock input of the integrated circuit memory device wherein the data input/output buffer controls writing and reading responsive to the internal clock signal, the internal clock generator being further configured to adjust a timing of the internal clock signal relative to the system clock signal responsive to the information of the selective mode register set command saved to the mode register.

8. An integrated circuit memory device according to claim 1 further comprising:

a plurality of data input/output pins wherein the data input/output buffer is configured to read data from the memory cell array to the data input/output pins during a read operation, wherein the data input/output buffer includes a plurality of output drivers with each of the output drivers being coupled to a respective one of the data input/output pins and wherein the output drivers are configured to adjust a strength thereof responsive to the information of the selective mode register set command saved to the mode register.